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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62812bf43b39c07824eb2f4d/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">第</div><div class="t m0 x2 h3 y3 ff1 fs0 fc1 sc0 ls0 ws0">第</div><div class="t m0 x3 h4 y4 ff2 fs0 fc0 sc0 ls0 ws0">2</div><div class="t m0 x4 h4 y3 ff2 fs0 fc1 sc0 ls0 ws0">2</div><div class="t m0 x5 h3 y5 ff1 fs0 fc0 sc1 ls0 ws0">章</div><div class="t m0 x6 h3 y3 ff1 fs0 fc1 sc2 ls0 ws0">章</div><div class="t m0 x7 h3 y5 ff1 fs0 fc0 sc1 ls0 ws0"> </div><div class="t m0 x8 h3 y3 ff1 fs0 fc2 sc3 ls0 ws0"> </div><div class="t m0 x9 h4 y4 ff2 fs0 fc3 sc0 ls0 ws0">FPGA/CPLD</div><div class="t m0 xa h4 y3 ff2 fs0 fc0 sc0 ls0 ws0">FPGA/CPLD</div><div class="t m0 xb h3 y5 ff1 fs0 fc3 sc4 ls0 ws0">器件</div><div class="t m0 xc h3 y3 ff1 fs0 fc0 sc1 ls0 ws0">器件</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62812bf43b39c07824eb2f4d/bg2.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 xd h5 y6 ff3 fs1 fc3 sc0 ls0 ws0">2.1 PLD</div><div class="t m0 xe h5 y7 ff3 fs1 fc0 sc0 ls0 ws0">2.1 PLD</div><div class="t m0 xf h6 y8 ff1 fs1 fc3 sc4 ls0 ws0">器件概述</div><div class="t m0 x10 h6 y7 ff1 fs1 fc0 sc1 ls0 ws0">器件概述</div><div class="t m0 xd h5 y9 ff3 fs1 fc3 sc0 ls0 ws0">2.2 PLD</div><div class="t m0 xe h5 ya ff3 fs1 fc0 sc0 ls0 ws0">2.2 PLD</div><div class="t m0 xf h6 yb ff1 fs1 fc3 sc4 ls0 ws0">的基本原理与结构</div><div class="t m0 x10 h6 ya ff1 fs1 fc0 sc1 ls0 ws0">的基本原理与结构</div><div class="t m0 xd h5 yc ff3 fs1 fc3 sc0 ls0 ws0">2.3 </div><div class="t m0 xe h5 yd ff3 fs1 fc0 sc0 ls0 ws0">2.3 </div><div class="t m0 x8 h6 ye ff1 fs1 fc3 sc4 ls0 ws0">低密度</div><div class="t m0 x11 h6 yd ff1 fs1 fc0 sc1 ls0 ws0">低密度</div><div class="t m0 x12 h5 yc ff3 fs1 fc3 sc0 ls0 ws0">PLD</div><div class="t m0 x13 h5 yd ff3 fs1 fc0 sc0 ls0 ws0">PLD</div><div class="t m0 x14 h6 ye ff1 fs1 fc3 sc4 ls0 ws0">的原理与结构</div><div class="t m0 x15 h6 yd ff1 fs1 fc0 sc1 ls0 ws0">的原理与结构</div><div class="t m0 xd h5 yf ff3 fs1 fc3 sc0 ls0 ws0">2.4 CPLD</div><div class="t m0 xe h5 y10 ff3 fs1 fc0 sc0 ls0 ws0">2.4 CPLD</div><div class="t m0 x16 h6 y11 ff1 fs1 fc3 sc4 ls0 ws0">的原理与结构</div><div class="t m0 x17 h6 y10 ff1 fs1 fc0 sc1 ls0 ws0">的原理与结构</div><div class="t m0 xd h5 y12 ff3 fs1 fc3 sc0 ls0 ws0">2.5 FPGA</div><div class="t m0 xe h5 y13 ff3 fs1 fc0 sc0 ls0 ws0">2.5 FPGA</div><div class="t m0 x16 h6 y14 ff1 fs1 fc3 sc4 ls0 ws0">的原理与结构</div><div class="t m0 x17 h6 y13 ff1 fs1 fc0 sc1 ls0 ws0">的原理与结构</div><div class="t m0 xd h5 y15 ff3 fs1 fc3 sc0 ls0 ws0">2.6 FPGA/C<span class="_ _0"></span>PLD</div><div class="t m0 xe h5 y16 ff3 fs1 fc0 sc0 ls0 ws0">2.6 FPGA/C<span class="_ _0"></span>PLD</div><div class="t m0 x18 h6 y17 ff1 fs1 fc3 sc4 ls0 ws0">的编程元件</div><div class="t m0 x19 h6 y16 ff1 fs1 fc0 sc1 ls0 ws0">的编程元件</div><div class="t m0 xd h5 y18 ff3 fs1 fc3 sc0 ls0 ws0">2.7 </div><div class="t m0 xe h5 y19 ff3 fs1 fc0 sc0 ls0 ws0">2.7 </div><div class="t m0 x8 h6 y1a ff1 fs1 fc3 sc4 ls0 ws0">边界扫描测试技<span class="_ _0"></span>术</div><div class="t m0 x11 h6 y19 ff1 fs1 fc0 sc1 ls0 ws0">边界扫描测试技<span class="_ _0"></span>术</div><div class="t m0 xd h5 y1b ff3 fs1 fc3 sc0 ls0 ws0">2.8 FPGA/C<span class="_ _0"></span>PLD</div><div class="t m0 xe h5 y1c ff3 fs1 fc0 sc0 ls0 ws0">2.8 FPGA/C<span class="_ _0"></span>PLD</div><div class="t m0 x18 h6 y1d ff1 fs1 fc3 sc4 ls0 ws0">的编程与配置</div><div class="t m0 x19 h6 y1c ff1 fs1 fc0 sc1 ls0 ws0">的编程与配置</div><div class="t m0 xd h5 y1e ff3 fs1 fc3 sc0 ls0 ws0">2.9 FPGA/C<span class="_ _0"></span>PLD</div><div class="t m0 xe h5 y1f ff3 fs1 fc0 sc0 ls0 ws0">2.9 FPGA/C<span class="_ _0"></span>PLD</div><div class="t m0 x18 h6 y20 ff1 fs1 fc3 sc4 ls0 ws0">器件概述</div><div class="t m0 x19 h6 y1f ff1 fs1 fc0 sc1 ls0 ws0">器件概述</div><div class="t m0 xd h5 y21 ff3 fs1 fc3 sc0 ls0 ws0">2.10 FPGA/CP<span class="_ _0"></span>LD</div><div class="t m0 xe h5 y22 ff3 fs1 fc0 sc0 ls0 ws0">2.10 FPGA/CP<span class="_ _0"></span>LD</div><div class="t m0 x1a h6 y23 ff1 fs1 fc3 sc4 ls0 ws0">的发展趋势 </div><div class="t m0 x1b h6 y22 ff1 fs1 fc0 sc1 ls0 ws0">的发展趋势 </div><div class="t m0 x1c h7 y24 ff1 fs2 fc0 sc1 ls0 ws0">内容</div><div class="t m0 x1d h7 y25 ff1 fs2 fc4 sc5 ls0 ws0">内容</div><div class="t m0 x1e h8 y26 ff1 fs3 fc1 sc0 ls0 ws0">第<span class="_ _1"> </span><span class="ff2">2<span class="_ _1"> </span></span><span class="sc2">章<span class="fc0 sc1"> <span class="_ _1"> </span><span class="ff2 sc0">FPGA/CPLD<span class="_ _2"> </span></span>器件<span class="fs4 sc0"> </span></span></span></div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62812bf43b39c07824eb2f4d/bg3.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1d h9 y27 ff2 fs3 fc0 sc0 ls0 ws0">2.1 <span class="ff4 fs5">PLD<span class="_ _2"> </span><span class="ff1 sc1">器<span class="_ _3"></span>件概述</span></span></div><div class="t m0 x1f h6 y28 ff3 fs1 fc5 sc0 ls0 ws0">PLD<span class="_ _4"> </span><span class="ff1 sc6">的发展历程 </span></div><div class="t m0 x20 ha y29 ff1 fs6 fc0 sc1 ls0 ws0">熔丝编程的</div><div class="t m0 x21 ha y2a ff4 fs6 fc0 sc0 ls0 ws0">PROM<span class="_ _5"> </span><span class="ff1">和</span></div><div class="t m0 x1 ha y2b ff4 fs6 fc0 sc0 ls0 ws0">PLA<span class="_ _5"> </span><span class="ff1 sc1">器件 </span></div><div class="t m0 x22 ha y2c ff4 fs6 fc0 sc0 ls0 ws0">AMD<span class="_ _5"> </span><span class="ff1 sc1">公</span></div><div class="t m0 x23 ha y2d ff1 fs6 fc0 sc1 ls0 ws0">司推出</div><div class="t m0 x24 ha y2e ff4 fs6 fc0 sc0 ls0 ws0">PAL<span class="_ _5"> </span><span class="ff1 sc1">器</span></div><div class="t m0 x25 ha y2f ff1 fs6 fc0 sc1 ls0 ws0">件 </div><div class="t m0 x26 ha y30 ff4 fs6 fc0 sc0 ls0 ws0">GAL<span class="_ _5"> </span><span class="ff1 sc1">器</span></div><div class="t m0 x27 ha y31 ff1 fs6 fc0 sc1 ls0 ws0">件 </div><div class="t m0 x28 ha y32 ff4 fs6 fc0 sc0 ls0 ws0">FPGA<span class="_ _5"> </span><span class="ff1 sc1">器</span></div><div class="t m0 x29 ha y33 ff1 fs6 fc0 sc1 ls0 ws0">件 </div><div class="t m0 x20 ha y34 ff4 fs6 fc0 sc0 ls0 ws0">EPLD<span class="_ _5"> </span><span class="ff1 sc1">器</span></div><div class="t m0 x29 ha y35 ff1 fs6 fc0 sc1 ls0 ws0">件 </div><div class="t m0 x2a ha y36 ff4 fs6 fc0 sc0 ls0 ws0">CPLD<span class="_ _5"> </span><span class="ff1 sc1">器</span></div><div class="t m0 x2b ha y37 ff1 fs6 fc0 sc1 ls0 ws0">件 </div><div class="t m0 x2c ha y38 ff1 fs6 fc0 sc1 ls0 ws0">内嵌复杂</div><div class="t m0 x2c ha y39 ff1 fs6 fc0 sc1 ls0 ws0">功能模块</div><div class="t m0 x2d ha y3a ff1 fs6 fc0 sc0 ls0 ws0">的<span class="_ _5"> </span><span class="ff4">SoPC </span></div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62812bf43b39c07824eb2f4d/bg4.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x2e hb y3b ff3 fs4 fc6 sc0 ls0 ws0"> <span class="_ _6"></span><span class="ff5">◆</span></div><div class="t m0 x2f hc y3c ff3 fs4 fc0 sc0 ls0 ws0"> </div><div class="t m0 x30 h6 y3b ff3 fs4 fc6 sc0 ls0 ws0"> <span class="fs1">1985<span class="_"> </span><span class="ff1 sc7">年，美<span class="_ _0"></span>国<span class="_ _4"> </span><span class="ff3 sc0">Xilinx<span class="_"> </span></span>公司<span class="_ _0"></span>推出了现场可编</span></span></div><div class="t m0 x31 h6 y3d ff1 fs1 fc6 sc7 ls0 ws0">程门阵列（<span class="_ _4"> </span><span class="ff3 sc0">F<span class="_ _0"></span>PGA<span class="_ _4"> </span><span class="ff1">，<span class="_ _4"> </span></span>Field Progr<span class="_ _0"></span>ammable </span></div><div class="t m0 x31 h6 y3e ff3 fs1 fc6 sc0 ls0 ws0">Gate Arr<span class="_ _0"></span>ay<span class="_"> </span><span class="ff1 sc7">）</span></div><div class="t m0 x1f h6 y13 ff3 fs1 fc6 sc0 ls0 ws0"> <span class="_ _7"></span><span class="ff1">◆<span class="_ _8"> </span><span class="ff3">CPLD<span class="_ _4"> </span></span>（<span class="_ _4"> </span><span class="ff3">Complex P<span class="_ _0"></span>rogrammable Logic </span></span></div><div class="t m0 x31 h6 y3f ff3 fs1 fc6 sc0 ls0 ws0">Device<span class="_ _4"> </span><span class="ff1 sc7">），即复<span class="_ _0"></span>杂可编程逻辑器<span class="_ _0"></span>件，是从</span></div><div class="t m0 x31 h6 y40 ff3 fs1 fc6 sc0 ls0 ws0">EPLD<span class="_ _4"> </span><span class="ff1 sc7">改进<span class="_ _0"></span>而来的。</span></div><div class="t m0 x1d h8 y41 ff2 fs3 fc0 sc0 ls0 ws0">PLD<span class="_ _1"> </span><span class="ff1 sc1">的发展</span></div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62812bf43b39c07824eb2f4d/bg5.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x32 h8 y42 ff2 fs3 fc0 sc0 ls0 ws0">PLD<span class="_ _1"> </span><span class="ff1 sc1">的集成度分类</span></div></div><div class="c x33 y43 w3 hd"><div class="t m1 x0 he y44 ff6 fs7 fc0 sc0 ls0 ws0"> </div></div><div class="c xa y45 w4 hf"><div class="t m1 x34 h10 y46 ff1 fs7 fc0 sc0 ls0 ws0">可编程逻辑器件（</div><div class="t m1 x35 he y47 ff6 fs7 fc0 sc0 ls0 ws0">P<span class="_ _3"></span>L<span class="_ _9"></span>D</div><div class="t m1 x36 h10 y46 ff1 fs7 fc0 sc0 ls0 ws0">）</div><div class="t m1 x37 he y47 ff6 fs7 fc0 sc0 ls0 ws0"> </div></div><div class="c x38 y48 w5 h11"><div class="t m1 x39 h10 y49 ff1 fs7 fc0 sc0 ls0 ws0">简单</div><div class="t m1 x2e he y4a ff6 fs7 fc0 sc0 ls0 ws0">P<span class="_ _3"></span>L<span class="_ _9"></span>D </div></div><div class="c x3a y48 w5 h11"><div class="t m1 x39 h10 y49 ff1 fs7 fc0 sc0 ls0 ws0">复杂</div><div class="t m1 x2e he y4a ff6 fs7 fc0 sc0 ls0 ws0">P<span class="_ _3"></span>L<span class="_ _9"></span>D </div></div><div class="c x3b y4b w6 h11"><div class="t m1 x3c he y4c ff6 fs7 fc0 sc0 ls0 ws0">P<span class="_ _3"></span>R<span class="_ _0"></span>O<span class="_ _0"></span>M<span class="_ _9"></span> </div></div><div class="c x3d y4b w7 h11"><div class="t m1 x3e he y4c ff6 fs7 fc0 sc0 ls0 ws0">P<span class="_ _a"></span>A<span class="_ _b"></span>L<span class="_ _9"></span> </div></div><div class="c x3f y4b w8 h11"><div class="t m1 x3b he y4d ff6 fs7 fc0 sc0 ls0 ws0">P<span class="_ _3"></span>L<span class="_ _9"></span>A<span class="_ _b"></span> </div></div><div class="c x40 y4b w7 h11"><div class="t m1 x3c he y4c ff6 fs7 fc0 sc0 ls0 ws0">GA<span class="_ _b"></span>L<span class="_ _9"></span> </div></div><div class="c x41 y4b w9 h11"><div class="t m1 x42 he y4c ff6 fs7 fc0 sc0 ls0 ws0">C<span class="_ _0"></span>PL<span class="_ _9"></span>D </div></div><div class="c x43 y4b w9 h11"><div class="t m1 x42 he y4c ff6 fs7 fc0 sc0 ls0 ws0">F<span class="_ _3"></span>P<span class="_ _3"></span>GA<span class="_ _b"></span> </div></div><div class="c x0 y1 w2 h2"><div class="t m0 x44 h6 y4e ff1 fs1 fc0 sc1 ls0 ws0">一般将<span class="_ _4"> </span><span class="ff3 sc0">GAL22V10<span class="_ _4"> </span><span class="ff1">（<span class="_ _4"> </span></span>500<span class="_ _4"> </span><span class="ff1">门<span class="_ _4"> </span></span>~750<span class="_"> </span></span>门 ）作<span class="_ _0"></span>为简单</div><div class="t m0 x44 h6 y4f ff3 fs1 fc0 sc0 ls0 ws0">PLD<span class="_ _4"> </span><span class="ff1 sc1">和高密度<span class="_ _4"> </span></span>P<span class="_ _0"></span>LD<span class="_ _4"> </span><span class="ff1 sc1">的分水岭</span></div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
