STM32 ISP 软件

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  • 2022-05-07 09:01
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使得STM32 MCU 可以象51一样用串口直接下载代码.
STM32 ISP.rar
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/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** * File Name : stm32f10x_rcc.c * Author : MCD Application Team * Version : V2.0.1 * Date : 06/13/2008 * Description : This file provides all the RCC firmware functions. ******************************************************************************** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *******************************************************************************/ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_rcc.h" /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define CR_OFFSET (RCC_OFFSET + 0x00) #define HSION_BitNumber 0x00 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) /* Alias word address of PLLON bit */ #define PLLON_BitNumber 0x18 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) /* Alias word address of CSSON bit */ #define CSSON_BitNumber 0x13 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) /* --- CFGR Register ---*/ /* Alias word address of USBPRE bit */ #define CFGR_OFFSET (RCC_OFFSET + 0x04) #define USBPRE_BitNumber 0x16 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) /* --- BDCR Register ---*/ /* Alias word address of RTCEN bit */ #define BDCR_OFFSET (RCC_OFFSET + 0x20) #define RTCEN_BitNumber 0x0F #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) /* Alias word address of BDRST bit */ #define BDRST_BitNumber 0x10 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define CSR_OFFSET (RCC_OFFSET + 0x24) #define LSION_BitNumber 0x00 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) /* ---------------------- RCC registers bit mask ------------------------ */ /* CR register bit mask */ #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF) #define CR_HSEBYP_Set ((u32)0x00040000) #define CR_HSEON_Reset ((u32)0xFFFEFFFF) #define CR_HSEON_Set ((u32)0x00010000) #define CR_HSITRIM_Mask ((u32)0xFFFFFF07) /* CFGR register bit mask */ #define CFGR_PLL_Mask ((u32)0xFFC0FFFF) #define CFGR_PLLMull_Mask ((u32)0x003C0000) #define CFGR_PLLSRC_Mask ((u32)0x00010000) #define CFGR_PLLXTPRE_Mask ((u32)0x00020000) #define CFGR_SWS_Mask ((u32)0x0000000C) #define CFGR_SW_Mask ((u32)0xFFFFFFFC) #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F) #define CFGR_HPRE_Set_Mask ((u32)0x000000F0) #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF) #define CFGR_PPRE1_Set_Mask ((u32)0x00000700) #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF) #define CFGR_PPRE2_Set_Mask ((u32)0x00003800) #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF) #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000) /* CSR register bit mask */ #define CSR_RMVF_Set ((u32)0x01000000) /* RCC Flag Mask */ #define FLAG_Mask ((u8)0x1F) /* Typical Value of the HSI in Hz */ #define HSI_Value ((u32)8000000) /* CIR register byte 2 (Bits[15:8]) base address */ #define CIR_BYTE2_ADDRESS ((u32)0x40021009) /* CIR register byte 3 (Bits[23:16]) base address */ #define CIR_BYTE3_ADDRESS ((u32)0x4002100A) /* CFGR register byte 4 (Bits[31:24]) base address */ #define CFGR_BYTE4_ADDRESS ((u32)0x40021007) /* BDCR register base address */ #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) /* Time out for HSE start up */ #define HSEStartUp_TimeOut ((u16)0x01FF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; static uc8 ADCPrescTable[4] = {2, 4, 6, 8}; static volatile FlagStatus HSEStatus; static vu32 StartUpCounter = 0; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /******************************************************************************* * Function Name : RCC_DeInit * Description : Resets the RCC clock configuration to the default reset state. * Input : None * Output : None * Return : None *******************************************************************************/ void RCC_DeInit(void) { /* Set HSION bit */ RCC->CR |= (u32)0x00000001; /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */ RCC->CFGR &= (u32)0xF8FF0000; /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (u32)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC->CR &= (u32)0xFFFBFFFF; /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ RCC->CFGR &= (u32)0xFF80FFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; } /******************************************************************************* * Function Name : RCC_HSEConfig * Description : Configures the External High Speed oscillator (HSE). * HSE can not be stopped if it is used directly or through the * PLL as system clock. * Input : - RCC_HSE: specifies the new state of the HSE. * This parameter can be one of the following values: * - RCC_HSE_OFF: HSE oscillator OFF * - RCC_HSE_ON: HSE oscillator ON * - RCC_HSE_Bypass: HSE oscillator bypassed with external * clock * Output : None * Return : None *******************************************************************************/ void RCC_HSEConfig(u32 RCC_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_HSE)); /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ /* Reset HSEON bit */ RCC->CR &= CR_HSEON_Reset; /* Reset HSEBYP bit */ RCC->CR &= CR_HSEBYP_Reset; /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ switch(RCC_HSE) { case RCC_HSE_ON: /* Set HSEON bit */ RCC->CR |= CR_HSEON_Set; break; case RCC_HSE_Bypass: /* Set HSEBYP and HSEON bits */ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; break; default: break; } } /******************************************************************************* * Function Name : RCC_WaitForHSEStartUp * Description : Waits for HSE start-up. * Input : None * Output : None * Return : An ErrorStatus enumuration value: * - SUCCE
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