S32K3 memory_S32K_源码/资料下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">S32K3 Memories Guide </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">1.<span class="_ _0"> </span><span class="ls0">Introduction</span></div><div class="t m0 x1 h4 y3 ff2 fs2 fc0 sc0 ls0 ws0">The purpose of this application note is to provide a </div><div class="t m0 x1 h4 y4 ff2 fs2 fc0 sc0 ls0 ws0">guideline to the readers about the memory features </div><div class="t m0 x1 h4 y5 ff2 fs2 fc0 sc0 ls0 ws0">included in the S32K3 Product Family. This document </div><div class="t m0 x1 h4 y6 ff2 fs2 fc0 sc0 ls0 ws0">details the available functions and best practice<span class="_ _1"></span>s for </div><div class="t m0 x1 h4 y7 ff2 fs2 fc0 sc0 ls0 ws0">running applications considering performance </div><div class="t m0 x1 h4 y8 ff2 fs2 fc0 sc0 ls0 ws0">improvements. </div><div class="t m0 x1 h4 y9 ff2 fs2 fc0 sc0 ls0 ws0">You can find four kinds of memories inside S32K3 </div><div class="t m0 x1 h4 ya ff2 fs2 fc0 sc0 ls0 ws0">Product Family, the Flash memory, the SRAM, the </div><div class="t m0 x1 h4 yb ff2 fs2 fc0 sc0 ls0 ws0">Tightly Coupled Memory (TCM) and the Cache </div><div class="t m0 x1 h4 yc ff2 fs2 fc0 sc0 ls0 ws0">Memory. The S32K3 Product Family also have some </div><div class="t m0 x1 h4 yd ff2 fs2 fc0 sc0 ls0 ws0">modules with dedicated memory such like EMAC and </div><div class="t m0 x1 h4 ye ff2 fs2 fc0 sc0 ls0 ws0">CAN. This document will mainly focus on Flash </div><div class="t m0 x1 h4 yf ff2 fs2 fc0 sc0 ls0 ws0">Memory, TCM and SRAM. </div><div class="t m0 x1 h4 y10 ff2 fs2 fc0 sc0 ls0 ws0">The Flash memory is dedicated for program code and </div><div class="t m0 x1 h4 y11 ff2 fs2 fc0 sc0 ls0 ws0">store data. Also, all devices in the family has a UTEST </div><div class="t m0 x1 h4 y12 ff2 fs2 fc0 sc0 ls0 ws0">sector of 8 KB for store important configurations or to </div><div class="t m0 x1 h4 y13 ff2 fs2 fc0 sc0 ls0 ws0">reserve information for the application. The S32K3 </div><div class="t m0 x1 h4 y14 ff2 fs2 fc0 sc0 ls0 ws0">Product Family has devices from 512 KB to 8 MB of </div><div class="t m0 x1 h4 y15 ff2 fs2 fc0 sc0 ls0 ws0">Flash program memory. </div><div class="t m0 x1 h4 y16 ff2 fs2 fc0 sc0 ls0 ws0">The RAM is integrated by the SRAM memory and the </div><div class="t m0 x1 h4 y17 ff2 fs2 fc0 sc0 ls0 ws0">TCM. Part of the SRAM memory is available in standby </div><div class="t m0 x1 h4 y18 ff2 fs2 fc0 sc0 ls0 ws0">mode. This means that the content of this memory are </div><div class="t m0 x1 h4 y19 ff2 fs2 fc0 sc0 ls0 ws0">retained after setting the MCU in standby mode. The </div><div class="t m0 x1 h4 y1a ff2 fs2 fc0 sc0 ls0 ws0">S32K3 product family leverages the TCM feature of </div><div class="t m0 x1 h4 y1b ff2 fs2 fc0 sc0 ls0 ws0">ARM Cortex M7 architecture, whose main purpose is to </div><div class="t m0 x1 h4 y1c ff2 fs2 fc0 sc0 ls0 ws0">provide a deterministic access time to the c<span class="_ _1"></span>ores to some </div><div class="t m0 x1 h4 y1d ff2 fs2 fc0 sc0 ls0 ws0">important data avoiding any delay in the acce<span class="_ _1"></span>ss. This </div><div class="t m0 x1 h4 y1e ff2 fs2 fc0 sc0 ls0 ws0">feature can be exploited in Real Time Operating </div><div class="t m0 x1 h4 y1f ff2 fs2 fc0 sc0 ls0 ws0">Systems. </div><div class="c x1 y20 w2 h5"><div class="t m0 x0 h6 y21 ff1 fs3 fc0 sc0 ls0 ws0">NXP Semiconductors<span class="_ _2"></span> </div></div><div class="c x1 y22 w2 h7"><div class="t m0 x0 h8 y23 ff3 fs3 fc0 sc0 ls0 ws0">Application Notes<span class="_ _2"></span> </div></div><div class="t m0 x2 h9 y24 ff3 fs2 fc0 sc0 ls0 ws1">Document <span class="ws0">Number:AN13388 </span></div><div class="t m0 x3 h9 y25 ff3 fs2 fc0 sc0 ls0 ws0">Rev. 0,<span class="ff4"> 11</span>/2021</div><div class="c x4 y26 w3 ha"><div class="t m0 x5 hb y27 ff1 fs4 fc0 sc0 ls0 ws0">Contents<span class="_ _2"></span> </div></div><div class="c x6 y28 w4 hc"><div class="t m0 x7 hd y29 ff2 fs5 fc1 sc0 ls2 ws0">1.<span class="_ _3"> </span><span class="ls0">Introduction <span class="_ _4"></span><span class="ls3">........................................................................<span class="ls0"> <span class="_ _5"></span>1</span></span></span></div><div class="t m0 x7 hd y2a ff2 fs5 fc1 sc0 ls2 ws0">2.<span class="_ _3"> </span><span class="ls0">Features <span class="_ _6"></span><span class="ls3">..............................................................................<span class="ls0"> <span class="_ _5"></span>2</span></span></span></div><div class="t m0 x7 hd y2b ff2 fs5 fc1 sc0 ls2 ws0">3.<span class="_ _3"> </span><span class="ls0">Flash memory <span class="ls3">....................................................................</span> <span class="_ _5"></span>3</span></div><div class="t m0 x8 hd y2c ff2 fs5 fc1 sc0 ls0 ws0">3.1.<span class="_ _7"> </span>Read <span class="_ _8"></span><span class="ls3">........................................................................<span class="ls0"> <span class="_ _5"></span>4</span></span></div><div class="t m0 x8 hd y2d ff2 fs5 fc1 sc0 ls0 ws0">3.2.<span class="_ _7"> </span>Write or Program <span class="_ _5"></span><span class="ls3">....................................................<span class="ls0"> <span class="_ _5"></span>4</span></span></div><div class="t m0 x8 hd y2e ff2 fs5 fc1 sc0 ls0 ws0">3.3.<span class="_ _7"> </span>Erase <span class="_ _5"></span><span class="ls3">.......................................................................<span class="ls0"> <span class="_ _1"></span>5</span></span></div><div class="t m0 x8 hd y2f ff2 fs5 fc1 sc0 ls0 ws0">3.4.<span class="_ _7"> </span>Locking and unlocking sector or super sector <span class="_ _6"></span><span class="ls3">.........<span class="ls0"> <span class="_ _1"></span>8</span></span></div><div class="t m0 x8 hd y30 ff2 fs5 fc1 sc0 ls0 ws0">3.5.<span class="_ _7"> </span>UTEST sector <span class="_ _1"></span><span class="ls3">.........................................................<span class="ls0"> <span class="_ _5"></span>9</span></span></div><div class="t m0 x7 hd y31 ff2 fs5 fc1 sc0 ls2 ws0">4.<span class="_ _3"> </span><span class="ls0">Tightly Coupled Memory <span class="_ _4"></span><span class="ls3">.................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">10</span></span></span></span></div><div class="t m0 x7 hd y32 ff2 fs5 fc1 sc0 ls2 ws0">5.<span class="_ _3"> </span><span class="ls0">SRAM <span class="_ _8"></span><span class="ls3">..............................................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">12</span></span></span></span></div><div class="t m0 x8 hd y33 ff2 fs5 fc1 sc0 ls0 ws0">5.1.<span class="_ _7"> </span>Read <span class="_ _8"></span><span class="ls3">......................................................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">14</span></span></span></div><div class="t m0 x8 hd y34 ff2 fs5 fc1 sc0 ls0 ws0">5.2.<span class="_ _7"> </span>Write <span class="_ _9"></span><span class="ls3">.....................................................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">14</span></span></span></div><div class="t m0 x7 hd y35 ff2 fs5 fc1 sc0 ls2 ws0">6.<span class="_ _3"> </span><span class="ls0">Use Cases <span class="_ _6"></span><span class="ls3">.........................................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">15</span></span></span></span></div><div class="t m0 x8 hd y36 ff2 fs5 fc1 sc0 ls0 ws0">6.1.<span class="_ _7"> </span>Flash vs TCM vs SRAM <span class="_ _6"></span><span class="ls3">.......................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">15</span></span></span></div><div class="t m0 x8 hd y37 ff2 fs5 fc1 sc0 ls0 ws0">6.2.<span class="_ _7"> </span>SRAM standby <span class="_ _4"></span><span class="ls3">......................................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">21</span></span></span></div><div class="t m0 x7 hd y38 ff2 fs5 fc1 sc0 ls2 ws0">7.<span class="_ _3"> </span><span class="ls0">SW recommendations and conclusions <span class="_ _6"></span><span class="ls3">............................<span class="ls0"> <span class="_ _1"></span><span class="ls2">26</span></span></span></span></div><div class="t m0 x7 hd y39 ff2 fs5 fc1 sc0 ls2 ws0">8.<span class="_ _3"> </span><span class="ls0">References <span class="_ _4"></span><span class="ls3">........................................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">26</span></span></span></span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return 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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/bg2.jpg"><div class="t m0 x1 he y3a ff1 fs6 fc0 sc0 ls0 ws0">Features </div><div class="t m0 x9 hf y3b ff1 fs5 fc0 sc0 ls0 ws0">S32K3 <span class="ws2">Memories </span>Guide, <span class="_ _2"></span>Rev. 0, <span class="ff5">11</span>/2021 </div><div class="t m0 x1 h10 y3c ff3 fs6 fc0 sc0 ls0 ws0">2<span class="fc2"> <span class="_ _a"> </span></span>NXP Semiconduc<span class="_ _1"></span>tors<span class="fc2"> </span></div><div class="t m0 x1 h4 y3d ff2 fs2 fc0 sc0 ls0 ws0">The Cache memory is a dedicated memory for the cores. This memory is not part of the system memory </div><div class="t m0 x1 h11 y3e ff6 fs2 fc0 sc0 ls0 ws0">and doesn’t have a physical address available for the programmer. This memory serves as an </div><div class="t m0 x1 h4 y3f ff2 fs2 fc0 sc0 ls0 ws0">intermediate buffer between the processor and the main memory to reduce memory access time for the </div><div class="t m0 x1 h4 y40 ff2 fs2 fc0 sc0 ls0 ws0">cores. </div><div class="t m0 x1 h3 y41 ff1 fs1 fc0 sc0 ls1 ws0">2.<span class="_ _b"> </span><span class="ls0">Features</span></div><div class="t m0 x1 h4 y42 ff2 fs2 fc0 sc0 ls0 ws0">S32K3 family devices memory features can be found in the <span class="ff7 fc3">Table 1</span> and <span class="ff7 fc3">2</span>. </div><div class="t m0 xa h12 y43 ff3 fs7 fc0 sc0 ls0 ws0">Table 1. <span class="_ _c"> </span><span class="ff1">S32K3 Memory featu<span class="_ _2"></span>res </span></div><div class="c xb y44 w5 h13"><div class="t m0 xc h14 y45 ff8 fs5 fc4 sc0 ls0 ws0">Feature </div></div><div class="c xd y44 w6 h13"><div class="t m0 xe h14 y46 ff8 fs5 fc4 sc0 ls0 ws0">S32K310 </div></div><div class="c xf y44 w7 h13"><div class="t m0 xe h14 y46 ff8 fs5 fc4 sc0 ls0 ws0">S32K311 </div></div><div class="c x10 y44 w8 h13"><div class="t m0 xe h14 y46 ff8 fs5 fc4 sc0 ls0 ws0">S32K341 </div></div><div class="c x11 y44 w9 h13"><div class="t m0 xe h14 y46 ff8 fs5 fc4 sc0 ls0 ws0">S32K312 </div></div><div class="c x12 y44 wa h13"><div class="t m0 xe h14 y46 ff8 fs5 fc4 sc0 ls0 ws0">S32K322 </div></div><div class="c x13 y44 wb h13"><div class="t m0 xe h14 y46 ff8 fs5 fc4 sc0 ls0 ws0">S32K342 </div></div><div class="c xb y47 w5 h15"><div class="t m0 xc h16 y48 ff9 fs5 fc0 sc0 ls0 ws0">Core qty </div></div><div class="c xd y47 wc h15"><div class="t m0 x14 h16 y48 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-<span class="ls4">M7</span> </div></div><div class="c xf y47 w9 h15"><div class="t m0 x14 h16 y48 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-<span class="ls4">M7</span> </div></div><div class="c x10 y47 wd h15"><div class="t m0 x14 h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-M7 </div><div class="t m0 x15 h16 y4a ff9 fs5 fc0 sc0 ls2 ws0">LS<span class="ls0"> </span></div></div><div class="c x11 y47 w9 h15"><div class="t m0 x14 h16 y48 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-<span class="ls4">M7</span> </div></div><div class="c x12 y47 wc h15"><div class="t m0 x14 h16 y48 ff9 fs5 fc0 sc0 ls0 ws0">2 x Cortex-<span class="ls4">M7</span> </div></div><div class="c x13 y47 we h15"><div class="t m0 x14 h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-M7 </div><div class="t m0 x15 h16 y4a ff9 fs5 fc0 sc0 ls2 ws0">LS<span class="ls0"> </span></div></div><div class="c xb y4b w5 h17"><div class="t m0 xc h16 y4c ff9 fs5 fc0 sc0 ls0 ws0">Program flash </div><div class="t m0 xc h16 y27 ff9 fs5 fc0 sc0 ls0 ws0">memory (MB) </div></div><div class="c xd y4b w6 h17"><div class="t m0 x8 h16 y4d ff9 fs5 fc0 sc0 ls5 ws0">512 KB<span class="ls0"> </span></div></div><div class="c xf y4b wf h17"><div class="t m0 x16 h16 y4d ff9 fs5 fc0 sc0 ls0 ws0">1 </div></div><div class="c x11 y4b w10 h17"><div class="t m0 x17 h16 y4d ff9 fs5 fc0 sc0 ls0 ws0">2 </div></div><div class="c xb y4e w5 h15"><div class="t m0 xc h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">Data flash </div><div class="t m0 xc h16 y4a ff9 fs5 fc0 sc0 ls0 ws0">memory (KB)</div><div class="t m0 x18 h18 y4f ff9 fs8 fc0 sc0 ls0 ws0">1 </div></div><div class="c xd y4e w11 h15"><div class="t m0 x19 h16 y50 ff9 fs5 fc0 sc0 ls5 ws0">64<span class="ls0"> </span></div></div><div class="c x10 y4e w12 h15"><div class="t m0 x1a h16 y50 ff9 fs5 fc0 sc0 ls5 ws0">128<span class="ls0"> </span></div></div><div class="c xb y51 w13 h19"><div class="t m0 xc h16 y52 ff9 fs5 fc0 sc0 ls0 ws0">Cache </div></div><div class="c xd y51 w14 h19"><div class="t m0 x1b h16 y53 ff9 fs5 fc0 sc0 ls0 ws0">I Cache 8 KB </div><div class="t m0 x1c h16 y54 ff9 fs5 fc0 sc0 ls0 ws0">D Cache 8 KB </div></div><div class="c xb y55 w13 h1a"><div class="t m0 xc h16 y56 ff9 fs5 fc0 sc0 ls0 ws0">Total RAM </div><div class="t m0 xc h16 y57 ff9 fs5 fc0 sc0 ls0 ws0">(KB) </div></div><div class="c xd y55 w15 h1a"><div class="t m0 x1d h16 y58 ff9 fs5 fc0 sc0 ls0 ws0">128 KB (including 96 KB TCM) </div></div><div class="c x10 y55 w6 h1a"><div class="t m0 x8 h16 y59 ff9 fs5 fc0 sc0 ls0 ws0">256 KB </div><div class="t m0 x14 h16 y58 ff9 fs5 fc0 sc0 ls0 ws0">(including 192 </div><div class="t m0 xe h16 y5a ff9 fs5 fc0 sc0 ls0 ws0">KB TCM) </div></div><div class="c x11 y55 w16 h1a"><div class="t m0 x8 h16 y59 ff9 fs5 fc0 sc0 ls5 ws0">192 KB<span class="ls0"> </span></div><div class="t m0 x1e h16 y58 ff9 fs5 fc0 sc0 ls0 ws0">(including <span class="ls5">96 </span></div><div class="t m0 xe h16 y5a ff9 fs5 fc0 sc0 ls0 ws0">KB TCM) </div></div><div class="c x12 y55 w11 h1a"><div class="t m0 x1f h16 y58 ff9 fs5 fc0 sc0 ls0 ws0">256 KB (including 192 KB TCM) </div></div><div class="c xb y5b w5 h1b"><div class="t m0 xc h16 y54 ff9 fs5 fc0 sc0 ls0 ws0">Standby RAM</div><div class="t m0 x1 h18 y5c ff9 fs8 fc0 sc0 ls0 ws0">2</div><div class="t m0 x20 h16 y54 ff9 fs5 fc0 sc0 ls0 ws0"> </div></div><div class="c xd y5b w17 h1b"><div class="t m0 x21 h16 y54 ff9 fs5 fc0 sc0 ls5 ws0">32 KB<span class="ls0"> </span></div></div><div class="t m0 xa h12 y5d ff3 fs7 fc0 sc0 ls0 ws0">Table 2. <span class="_ _c"> </span><span class="ff1">S32K3 Memory featu<span class="_ _2"></span>res </span></div><div class="c x22 y5e w18 h1b"><div class="t m0 xc h14 y45 ff8 fs5 fc4 sc0 ls0 ws0">Feature </div></div><div class="c x23 y5e w19 h1b"><div class="t m0 x1d h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K314 </div></div><div class="c x24 y5e w1a h1b"><div class="t m0 x1e h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K324 </div></div><div class="c x25 y5e w1b h1b"><div class="t m0 x1e h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K344 </div></div><div class="c x26 y5e w1c h1b"><div class="t m0 x27 h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K328 </div></div><div class="c x28 y5e w1d h1b"><div class="t m0 x27 h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K348 </div></div><div class="c x29 y5e w1e h1b"><div class="t m0 x27 h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K338 </div></div><div class="c x2a y5e w1f h1b"><div class="t m0 x2b h14 y54 ff8 fs5 fc4 sc0 ls0 ws0">S32K358 </div></div><div class="c x22 y5f w18 h15"><div class="t m0 xc h16 y48 ff9 fs5 fc0 sc0 ls0 ws0">Core qty </div></div><div class="c x23 y5f w19 h15"><div class="t m0 x1e h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-</div><div class="t m0 x2b h16 y4a ff9 fs5 fc0 sc0 ls4 ws0">M7<span class="ls0"> </span></div></div><div class="c x24 y5f w20 h15"><div class="t m0 x2c h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">2 x Cortex-</div><div class="t m0 x8 h16 y4a ff9 fs5 fc0 sc0 ls4 ws0">M7<span class="ls0"> </span></div></div><div class="c x25 y5f w21 h15"><div class="t m0 x2c h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-</div><div class="t m0 x2d h16 y4a ff9 fs5 fc0 sc0 ls0 ws0">M7 LS </div></div><div class="c x26 y5f w22 h15"><div class="t m0 x7 h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">2 x Cortex-</div><div class="t m0 x2e h16 y4a ff9 fs5 fc0 sc0 ls4 ws0">M7<span class="ls0"> </span></div></div><div class="c x28 y5f w23 h15"><div class="t m0 x7 h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-</div><div class="t m0 xe h16 y4a ff9 fs5 fc0 sc0 ls0 ws0">M7 LS </div></div><div class="c x29 y5f w1e h15"><div class="t m0 x7 h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">3 x Cortex-</div><div class="t m0 x2e h16 y4a ff9 fs5 fc0 sc0 ls4 ws0">M7<span class="ls0"> </span></div></div><div class="c x2a y5f w24 h15"><div class="t m0 x2f h16 y49 ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-M7 LS + </div><div class="t m0 x30 h16 y4a ff9 fs5 fc0 sc0 ls0 ws0">1 x Cortex-<span class="ls4">M7</span> </div></div><div class="c x22 y60 w18 h17"><div class="t m0 xc h16 y4c ff9 fs5 fc0 sc0 ls0 ws0">Program flash </div><div class="t m0 xc h16 y27 ff9 fs5 fc0 sc0 ls0 ws0">memory (MB) </div></div><div class="c x23 y60 w25 h17"><div class="t m0 x31 h16 y61 ff9 fs5 fc0 sc0 ls0 ws0">4 </div></div><div class="c x26 y60 w26 h17"><div class="t m0 x23 h16 y61 ff9 fs5 fc0 sc0 ls0 ws0">8 </div></div><div class="c x22 y62 w18 h1c"><div class="t m0 xc h16 y63 ff9 fs5 fc0 sc0 ls0 ws0">Data flash </div><div class="t m0 xc h16 y21 ff9 fs5 fc0 sc0 ls0 ws0">memory (KB)</div><div class="t m0 x18 h18 y64 ff9 fs8 fc0 sc0 ls0 ws0">1</div><div class="t m0 x32 h16 y21 ff9 fs5 fc0 sc0 ls0 ws0"> </div></div><div class="c x23 y62 w27 h1c"><div class="t m0 x33 h16 y65 ff9 fs5 fc0 sc0 ls5 ws0">128<span class="ls0"> </span></div></div><div class="c x22 y66 w28 h1d"><div class="t m0 xc h16 y67 ff9 fs5 fc0 sc0 ls0 ws0">Cache </div></div><div class="c x23 y66 w29 h1d"><div class="t m0 x22 h16 y68 ff9 fs5 fc0 sc0 ls0 ws0">I Cache 8 KB </div><div class="t m0 x34 h16 y69 ff9 fs5 fc0 sc0 ls0 ws0">D Cache 8 KB </div></div><div class="c x26 y66 w26 h1d"><div class="t m0 x35 h16 y67 ff9 fs5 fc0 sc0 ls0 ws0">TBD </div></div><div class="c x22 y6a w18 h1e"><div class="t m0 xc h16 y6b ff9 fs5 fc0 sc0 ls0 ws0">Total RAM </div><div class="t m0 xc h16 y6c ff9 fs5 fc0 sc0 ls0 ws0">(KB) </div></div><div class="c x23 y6a w2a h1e"><div class="t m0 x36 h16 y6d ff9 fs5 fc0 sc0 ls5 ws0">512 KB<span class="ls0"> </span></div><div class="t m0 x1f h16 y6b ff9 fs5 fc0 sc0 ls0 ws0">(including </div><div class="t m0 x37 h16 y6c ff9 fs5 fc0 sc0 ls5 ws0">96 KB<span class="ls0"> </span></div><div class="t m0 x37 h16 y54 ff9 fs5 fc0 sc0 ls0 ws0">TCM) </div></div><div class="c x24 y6a w2b h1e"><div class="t m0 x38 h16 y6b ff9 fs5 fc0 sc0 ls0 ws0">512 KB (including </div><div class="t m0 x15 h16 y6c ff9 fs5 fc0 sc0 ls0 ws0">192 KB TCM) </div></div><div class="c x26 y6a w2c h1e"><div class="t m0 x1e h16 y6b ff9 fs5 fc0 sc0 ls0 ws0">1152 KB (including 192 KB </div><div class="t m0 x39 h16 y6c ff9 fs5 fc0 sc0 ls0 ws0">TCM) </div></div><div class="c x29 y6a w2d h1e"><div class="t m0 x1f h16 y6e ff9 fs5 fc0 sc0 ls0 ws0">1152 KB (including 384 KB TCM) </div></div><div class="c x22 y6f w18 h1b"><div class="t m0 xc h16 y70 ff9 fs5 fc0 sc0 ls0 ws0">Standby RAM</div><div class="t m0 x1 h1f y71 ff9 fs9 fc0 sc0 ls0 ws0">2</div><div class="t m0 x20 h16 y70 ff9 fs5 fc0 sc0 ls0 ws0"> </div></div><div class="c x23 y6f w25 h1b"><div class="t m0 x3a h16 y72 ff9 fs5 fc0 sc0 ls5 ws0">32 KB<span class="ls0"> </span></div></div><div class="c x26 y6f w26 h1b"><div class="t m0 x3b h16 y72 ff9 fs5 fc0 sc0 ls5 ws0">64 KB<span class="ls0"> </span></div></div><div class="c x22 y73 w2e h20"><div class="t m0 xc h21 y74 ff3 fs5 fc0 sc0 ls6 ws0">1.<span class="_ _d"> </span><span class="ls0">This represents the maximum available Data Flash memory. Refer to the S32K3 <span class="_ _2"></span>Ref<span class="_ _1"></span>erence Manual for limitations</span></div><div class="t m0 x2e h21 y75 ff3 fs5 fc0 sc0 ls0 ws0">applying when HSE security firmware is installed</div><div class="t m0 xc h21 y76 ff3 fs5 fc0 sc0 ls6 ws0">2.<span class="_ _d"> </span><span class="ls0">The Standby RAM is also included in the Total RAM</span></div></div><div class="t m0 x1 h4 y77 ff2 fs2 fc0 sc0 ls0 ws0">An important feature to remark is that all memories inside the S32K3 Product Family has Error </div><div class="t m0 x1 h4 y78 ff2 fs2 fc0 sc0 ls0 ws0">Detection and Error Correction Code. </div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/bg3.jpg"><div class="t m0 x3c he y3a ff1 fs6 fc0 sc0 ls0 ws0">Flash memory<span class="_ _1"></span> </div><div class="t m0 x1 h10 y79 ff3 fs6 fc2 sc0 ls0 ws0">NXP Semiconduc<span class="_ _1"></span>tors <span class="_ _a"> </span>3 </div><div class="t m0 x1 h3 y7a ff1 fs1 fc0 sc0 ls1 ws0">3.<span class="_ _b"> </span><span class="ls0">Flash memory</span></div><div class="t m0 x1 h4 y7b ff2 fs2 fc0 sc0 ls0 ws0">The flash memory on S32K3 devices is integrated by blocks. There are five blocks as maximum and two </div><div class="t m0 x1 h4 y7c ff2 fs2 fc0 sc0 ls0 ws0">blocks as minimum. Detailed information is provided in the following table. </div><div class="t m0 x3d h12 y7d ff3 fs7 fc0 sc0 ls0 ws0">Table 3. <span class="_ _c"> </span><span class="ff1">Flash memory archit<span class="_ _2"></span>ecture for S32K3<span class="_ _2"></span> </span></div><div class="c x16 y7e w2f h22"><div class="t m0 x3e h14 y7f ff8 fs5 fc4 sc0 ls0 ws0">Flash Blocks </div></div><div class="c x24 y7e w30 h22"><div class="t m0 x37 h14 y7f ff8 fs5 fc4 sc0 ls0 ws0">S32K310 </div></div><div class="c x3f y7e w31 h22"><div class="t m0 x37 h14 y80 ff8 fs5 fc4 sc0 ls0 ws0">S32K311 </div><div class="t m0 x37 h14 y4d ff8 fs5 fc4 sc0 ls0 ws0">S32K341 </div></div><div class="c x40 y7e w32 h22"><div class="t m0 x37 h14 y81 ff8 fs5 fc4 sc0 ls0 ws0">S32K312 </div><div class="t m0 x37 h14 y7f ff8 fs5 fc4 sc0 ls0 ws0">S32K322 </div><div class="t m0 x37 h14 y27 ff8 fs5 fc4 sc0 ls0 ws0">S32K342 </div></div><div class="c x41 y7e w31 h22"><div class="t m0 x37 h14 y81 ff8 fs5 fc4 sc0 ls0 ws0">S32K314 </div><div class="t m0 x37 h14 y7f ff8 fs5 fc4 sc0 ls0 ws0">S32K324 </div><div class="t m0 x37 h14 y27 ff8 fs5 fc4 sc0 ls0 ws0">S32K344 </div></div><div class="c x13 y7e w30 h22"><div class="t m0 x37 h14 y82 ff8 fs5 fc4 sc0 ls0 ws0">S32K328 </div><div class="t m0 x37 h14 y80 ff8 fs5 fc4 sc0 ls0 ws0">S32K338 </div><div class="t m0 x37 h14 y4d ff8 fs5 fc4 sc0 ls0 ws0">S32K348 </div><div class="t m0 x37 h14 y83 ff8 fs5 fc4 sc0 ls0 ws0">S32K358 </div></div><div class="c x16 y84 w33 h23"><div class="t m0 x17 h18 y85 ff9 fs8 fc0 sc0 ls0 ws0">End </div><div class="t m0 x42 h18 y86 ff9 fs8 fc0 sc0 ls0 ws0">Address</div><div class="t m0 x43 h24 y87 ff9 fs2 fc0 sc0 ls0 ws0">UTEST </div><div class="t m0 x44 h18 y88 ff9 fs8 fc0 sc0 ls0 ws0"> Start Address</div></div><div class="c x24 y84 w34 h23"><div class="t m0 xc h18 y89 ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_1FFF </div><div class="t m0 x45 h25 y8a ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">8 KB<span class="fs8"> </span></span></div><div class="t m0 xc h18 y8b ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_0000 </div></div><div class="c x3f y84 w35 h23"><div class="t m0 xc h18 y89 ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_1FFF </div><div class="t m0 x45 h25 y8a ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">8 KB<span class="fs8"> </span></span></div><div class="t m0 xc h18 y8b ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_0000 </div></div><div class="c x40 y84 w34 h23"><div class="t m0 xc h18 y89 ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_1FFF </div><div class="t m0 x45 h25 y8a ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">8 KB<span class="fs8"> </span></span></div><div class="t m0 xc h18 y8b ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_0000 </div></div><div class="c x41 y84 w35 h23"><div class="t m0 xc h18 y89 ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_1FFF </div><div class="t m0 x45 h25 y8a ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">8 KB<span class="fs8"> </span></span></div><div class="t m0 xc h18 y8b ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_0000 </div></div><div class="c x13 y84 w36 h23"><div class="t m0 xc h18 y89 ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_1FFF </div><div class="t m0 x45 h25 y8a ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">8 KB<span class="fs8"> </span></span></div><div class="t m0 xc h18 y8b ff9 fs8 fc0 sc0 ls0 ws0">0x1B00_0000 </div></div><div class="c x16 y8c w33 h26"><div class="t m0 x17 h18 y8d ff9 fs8 fc0 sc0 ls0 ws0">End </div><div class="t m0 x42 h18 y8e ff9 fs8 fc0 sc0 ls0 ws0">Address</div><div class="t m0 x46 h24 y8f ff9 fs2 fc0 sc0 ls0 ws0">Block4 </div><div class="t m0 x27 h24 y90 ff9 fs2 fc0 sc0 ls0 ws0">Data Flash Memory </div><div class="t m0 x44 h18 y91 ff9 fs8 fc0 sc0 ls0 ws0"> Start Address</div></div><div class="c x24 y8c w34 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">64 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_0000 </div></div><div class="c x3f y8c w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">64 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_0000 </div></div><div class="c x40 y8c w34 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x1001_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">128 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_0000 </div></div><div class="c x41 y8c w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x1001_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">128 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_0000 </div></div><div class="c x13 y8c w36 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x1001_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">128 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x1000_0000 </div></div><div class="c x16 y95 w33 h26"><div class="t m0 x17 h18 y8d ff9 fs8 fc0 sc0 ls0 ws0">End </div><div class="t m0 x42 h18 y8e ff9 fs8 fc0 sc0 ls0 ws0">Address</div><div class="t m0 x46 h24 y8f ff9 fs2 fc0 sc0 ls0 ws0">Block3 </div><div class="t m0 x2c h24 y90 ff9 fs2 fc0 sc0 ls0 ws0">Code Flash Memory 3 </div><div class="t m0 x44 h18 y91 ff9 fs8 fc0 sc0 ls0 ws0"> Start Address</div></div><div class="c x24 y95 w34 h26"><div class="t m0 x47 h24 y96 ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x3f y95 w35 h26"><div class="t m0 x47 h24 y96 ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x40 y95 w34 h26"><div class="t m0 x47 h24 y96 ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x41 y95 w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x007F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">1 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0070_0000 </div></div><div class="c x13 y95 w36 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x00BF_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">2 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x00A0_0000 </div></div><div class="c x16 y98 w33 h27"><div class="t m0 x17 h18 y99 ff9 fs8 fc0 sc0 ls0 ws0">End </div><div class="t m0 x42 h18 y9a ff9 fs8 fc0 sc0 ls0 ws0">Address</div><div class="t m0 x46 h24 y8f ff9 fs2 fc0 sc0 ls0 ws0">Block2 </div><div class="t m0 x2c h24 y90 ff9 fs2 fc0 sc0 ls0 ws0">Code Flash Memory 2 </div><div class="t m0 x44 h18 y91 ff9 fs8 fc0 sc0 ls0 ws0"> Start Address</div></div><div class="c x24 y98 w34 h27"><div class="t m0 x47 h24 y9b ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x3f y98 w35 h27"><div class="t m0 x47 h24 y9b ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x40 y98 w34 h27"><div class="t m0 x47 h24 y9b ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x41 y98 w35 h27"><div class="t m0 xc h18 y9c ff9 fs8 fc0 sc0 ls0 ws0">0x006F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">1 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0060_0000 </div></div><div class="c x13 y98 w36 h27"><div class="t m0 xc h18 y9c ff9 fs8 fc0 sc0 ls0 ws0">0x009F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">2 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0080_0000 </div></div><div class="c x16 y9d w33 h26"><div class="t m0 x17 h18 y8d ff9 fs8 fc0 sc0 ls0 ws0">End </div><div class="t m0 x42 h18 y8e ff9 fs8 fc0 sc0 ls0 ws0">Address</div><div class="t m0 x46 h24 y8f ff9 fs2 fc0 sc0 ls0 ws0">Block1 </div><div class="t m0 x2c h24 y90 ff9 fs2 fc0 sc0 ls0 ws0">Code Flash Memory 1 </div><div class="t m0 x44 h18 y91 ff9 fs8 fc0 sc0 ls0 ws0"> Start Address</div></div><div class="c x24 y9d w34 h26"><div class="t m0 x47 h24 y96 ff9 fs2 fc0 sc0 ls0 ws0">Not </div><div class="t m0 x27 h24 y97 ff9 fs2 fc0 sc0 ls0 ws0">Available </div></div><div class="c x3f y9d w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x004F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">512 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0048_0000 </div></div><div class="c x40 y9d w34 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x005F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">1 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0050_0000 </div></div><div class="c x41 y9d w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x005F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">1 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0050_0000 </div></div><div class="c x13 y9d w36 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x007F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">2 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0060_0000 </div></div><div class="c x16 y9e w33 h26"><div class="t m0 x17 h18 y8d ff9 fs8 fc0 sc0 ls0 ws0">End </div><div class="t m0 x42 h18 y8e ff9 fs8 fc0 sc0 ls0 ws0">Address</div><div class="t m0 x46 h24 y8f ff9 fs2 fc0 sc0 ls0 ws0">Block0 </div><div class="t m0 x2c h24 y90 ff9 fs2 fc0 sc0 ls0 ws0">Code Flash Memory 0 </div><div class="t m0 x44 h18 y91 ff9 fs8 fc0 sc0 ls0 ws0"> Start Address</div></div><div class="c x24 y9e w34 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x0047_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">512 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0040_0000 </div></div><div class="c x3f y9e w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x0047_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">512 KB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0040_0000 </div></div><div class="c x40 y9e w34 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x004F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">1 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0040_0000 </div></div><div class="c x41 y9e w35 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x004F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">1 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0040_0000 </div></div><div class="c x13 y9e w36 h26"><div class="t m0 xc h18 y92 ff9 fs8 fc0 sc0 ls0 ws0">0x005F_FFFF </div><div class="t m0 x45 h25 y93 ff9 fs7 fc0 sc0 ls7 ws0"> <span class="ls0">2 MB </span></div><div class="t m0 xc h18 y94 ff9 fs8 fc0 sc0 ls0 ws0">0x0040_0000 </div></div><div class="t m0 x1 h4 y9f ff2 fs2 fc0 sc0 ls0 ws0">In the S32K3 Product Family <span class="ws3">the </span>device<span class="ws4">s </span>are <span class="ws5">a</span>vailable from 512 KB to 8 MB of Flash memory. The </div><div class="t m0 x1 h4 ya0 ff7 fs2 fc3 sc0 ls0 ws0">Table 3<span class="ff2 fc0 ws4"> <span class="ws0">classifies the S32K3 Product Family devices by Flash memory size. </span></span></div><div class="t m0 x1 h4 ya1 ff2 fs2 fc0 sc0 ls0 ws0">There are <span class="ws6">som</span>e regions <span class="ws7">i</span>nside the <span class="ws8">F</span>lash memory that are <span class="ws5">p</span>rotected to be used by the a<span class="_ _1"></span>pplication cores. </div><div class="t m0 x1 h4 ya2 ff2 fs2 fc0 sc0 ls0 ws0">These <span class="ws8">a</span>re only available for <span class="ws9">HSE_B <span class="wsa">c</span></span>ore<span class="wsb">. </span>For more <span class="ws5">infor</span>mation about HSE_B refer to S32K3 Reference </div><div class="t m0 x1 h4 ya3 ff2 fs2 fc0 sc0 ls0 ws0">Manual. </div><div class="t m0 x1 h4 ya4 ff2 fs2 fc0 sc0 ls0 ws0">There are three operations modes for the Flash memory. When the device <span class="ws5">i</span>s working in User mode <span class="wsc">t</span>he </div><div class="t m0 x1 h4 ya5 ff2 fs2 fc0 sc0 ls0 ws0">Flash memory array is accessible to execute a <span class="ws9">r</span>ea<span class="_ _1"></span>d, program or erase <span class="wsd">ope</span>ration. The <span class="wsc">Use</span>r mode is the </div><div class="t m0 x1 h4 ya6 ff2 fs2 fc0 sc0 ls0 ws0">default <span class="wsa">ope</span>rating mode of the <span class="wsc">F</span>lash memory. A<span class="ls8 wse">ll the </span>registers have <span class="ws5">r</span>ead a<span class="_ _1"></span>nd write <span class="ws5">a</span>cce<span class="wsf">ss. </span>I<span class="_ _1"></span>n low power </div><div class="t m0 x1 h4 ya7 ff2 fs2 fc0 sc0 ls0 ws0">mode the <span class="ws5">F</span>lash memory is not <span class="ws7">a</span>ccessible beca<span class="_ _1"></span>use <span class="ws5">it</span>s power source is turned <span class="wsb">off</span>, so operations are <span class="ws6">not </span></div><div class="t m0 x1 h4 ya8 ff2 fs2 fc0 sc0 ls0 ws0">allowed in this mode. Finally the <span class="ws5">Ute</span>st mode is a te<span class="_ _1"></span>st mode <span class="ws5">whe</span>re the integrity of the Flash me<span class="ws10">mory </span>can </div><div class="t m0 x1 h4 ya9 ff2 fs2 fc0 sc0 ls0 ws0">be <span class="ws5">verified. </span></div><div class="t m0 x48 hf yaa ff1 fs5 fc0 sc0 ls0 ws0">S32K3 <span class="ws2">Memories </span>Guide, <span class="_ _2"></span>Rev. <span class="ws2">0, </span><span class="ffa">11</span>/2021 </div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/bg4.jpg"><div class="t m0 x1 he y3a ff1 fs6 fc0 sc0 ls0 ws0">Flash memory<span class="_ _1"></span> </div><div class="t m0 x1 h10 y3c ff3 fs6 fc0 sc0 ls0 ws0">4<span class="fc2"> <span class="_ _a"> </span></span>NXP Semiconduc<span class="_ _1"></span>tors<span class="fc2"> </span></div><div class="t m0 x1 h4 y3d ff2 fs2 fc0 sc0 ls0 ws0">The Flash memory can perform multiple reads between differe<span class="_ _1"></span>nt blocks by a single, dual or quad read </div><div class="t m0 x1 h4 y3e ff2 fs2 fc0 sc0 ls0 ws0">feature, where in a multi-core scenario, if there are multiple threads running in parallel (on differe<span class="_ _1"></span>nt </div><div class="t m0 x1 h4 y3f ff2 fs2 fc0 sc0 ls0 ws0">sections/blocks of memory) those threads can occur simultaneously by a dual or quad rea<span class="_ _1"></span>d, this feature </div><div class="t m0 x1 h4 y40 ff6 fs2 fc0 sc0 ls0 ws0">is controlled internally and not by the user. It also has the “Read<span class="ff2">-While-</span>Write” (RWW) feature to be </div><div class="t m0 x1 h4 yab ff2 fs2 fc0 sc0 ls0 ws0">able to perform a read and a write simultaneously (a<span class="_ _1"></span>pplies only when operations are in different blocks); </div><div class="t m0 x1 h4 yac ff2 fs2 fc0 sc0 ls0 ws0">for example, in the S32K324, if the Core 0 application is performing a<span class="_ _1"></span> write process in block 0, then the </div><div class="t m0 x1 h4 yad ff2 fs2 fc0 sc0 ls0 ws0">Core 1 at the same time can rea<span class="_ _1"></span>d a data stored in the data flash block. <span class="_ _2"></span> </div><div class="t m0 x1 h4 y1 ff2 fs2 fc0 sc0 ls0 ws0">There are four important operations that we need to consider when we are working with the Flash </div><div class="t m0 x1 h4 yae ff2 fs2 fc0 sc0 ls0 ws0">memory: </div><div class="t m0 x49 h4 yaf ffb fs2 fc0 sc0 ls0 ws0">•<span class="_"> </span><span class="ff2">Read Flash memory</span></div><div class="t m0 x49 h4 yb0 ffb fs2 fc0 sc0 ls0 ws0">•<span class="_"> </span><span class="ff2">Lock and Unlock sector or super sector</span></div><div class="t m0 x49 h4 yb1 ffb fs2 fc0 sc0 ls0 ws0">•<span class="_"> </span><span class="ff2">Program Flash memory</span></div><div class="t m0 x49 h4 yb2 ffb fs2 fc0 sc0 ls0 ws0">•<span class="_"> </span><span class="ff2">Erase Flash memory</span></div><div class="t m0 x1 h28 yb3 ff3 fsa fc0 sc0 ls0 ws0">3.1. </div><div class="t m0 x4a h29 yb4 ff1 fsa fc0 sc0 ls0 ws0">Read </div><div class="t m0 x1 h4 yb5 ff2 fs2 fc0 sc0 ls0 ws0">After <span class="wsc">r</span>eset, the Flash memory is in a <span class="ws5">de</span>fault <span class="wsa">state </span>which have <span class="_ _1"></span><span class="ws11">the <span class="ws0">arrays an<span class="ws12">d </span>register available to be rea<span class="_ _1"></span>d </span></span></div><div class="t m0 x1 h4 yb6 ff2 fs2 fc0 sc0 ls0 ws0">by the controller. A <span class="wsc">r</span>ea<span class="wsb">d </span>opera<span class="_ _1"></span>tion fr<span class="wsf">om </span>Flash memory return a <span class="_ _1"></span>256 bits of data length and register reads </div><div class="t m0 x1 h4 yb7 ff2 fs2 fc0 sc0 ls0 ws0">return 32 bits. For this operation is not necessary to consider a <span class="ws6">Lo</span>ck or Unlock sector. The <span class="ws5">re</span>ad </div><div class="t m0 x1 h4 yb8 ff2 fs2 fc0 sc0 ls0 ws0">operation is performed by the PFlash controller which is the <span class="ws5">int</span>erfa<span class="_ _1"></span>ce <span class="ws5">be</span>tween the system bus and the </div><div class="t m0 x1 h4 yb9 ff2 fs2 fc0 sc0 ls0 ws0">embedde<span class="wsb">d </span>Flash memory. </div><div class="t m0 x1 h28 yba ff3 fsa fc0 sc0 ls0 ws0">3.2. </div><div class="t m0 x4a h29 ybb ff1 fsa fc0 sc0 ls0 ws0">Write <span class="ws13">or </span>Program </div><div class="t m0 x1 h4 ybc ff2 fs2 fc0 sc0 ls0 ws0">The <span class="wsc">mi</span>nimum program size is 2 words (64 bits) and data must <span class="ws7">be </span>64 bit <span class="wsa">a<span class="_ _1"></span><span class="ws0">ligned. A maximum of 4 pages </span></span></div><div class="t m0 x1 h4 ybd ff2 fs2 fc0 sc0 ls0 ws0">can be <span class="ws5">prog</span>ramme<span class="wsb">d </span>at the <span class="ws5">sa<span class="_ _1"></span><span class="ws0">me time<span class="ws14">, </span>where 1 page <span class="ws5">a</span>re <span class="wsb">8 </span>wor<span class="_ _1"></span>ds (256 bits<span class="wsd">). </span>This mean that up to 1024 </span></span></div><div class="t m0 x1 h4 ybe ff2 fs2 fc0 sc0 ls0 ws0">bits can be <span class="ws5">a</span>ltered in a single program operati<span class="wsb">on. </span>Whe<span class="_ _1"></span>n a <span class="ws5">prog</span>ram operation or <span class="ws8">wr</span>ite <span class="ws5">ope</span>ration is made </div><div class="t m0 x1 h4 ybf ff2 fs2 fc0 sc0 ls0 ws0">the ECC <span class="ws7">bit</span>s are <span class="ws6">c</span>alculated and store<span class="_ _1"></span>d. The <span class="ws5">ECC </span>is handled on 64 bits doubleword. Eight <span class="ws7">bi<span class="_ _2"></span></span>ts of ECC </div><div class="t m0 x1 h4 yc0 ff2 fs2 fc0 sc0 ls0 ws0">are <span class="ws6">ne</span>eded. </div><div class="t m0 x1 h4 yc1 ff2 fs2 fc0 sc0 ls0 ws0">A program operation changes the logic <span class="ws5">va</span>lue of a bit <span class="wsa">fr</span>om 1 to 0, this means that a pr<span class="_ _1"></span>ogram operation </div><div class="t m0 x1 h4 yc2 ff2 fs2 fc0 sc0 ls0 ws0">from 0 to 1 is not allowed and the Flash me<span class="_ _1"></span>mo<span class="wsd">ry </span>needs to be <span class="ws5">e</span>rased before <span class="ws15">a</span>ny program operation. </div><div class="t m0 x1 h4 yc3 ff2 fs2 fc0 sc0 ls0 ws0">When da<span class="ws11">ta </span>Flash is used for <span class="ws9">EEPR</span>OM emulation, approved drivers by NXP <span class="wsa">c</span>an do a<span class="_ _1"></span>n over-</div><div class="t m0 x1 h4 yc4 ff2 fs2 fc0 sc0 ls0 ws0">programming in a 64 bit <span class="wsa">ECC <span class="ws16">se</span></span>gment, this allows to over-program the <span class="ws5">sa</span>me loca<span class="_ _1"></span>tion up to 3 times </div><div class="t m0 x1 h4 yc5 ff2 fs2 fc0 sc0 ls0 ws0">without <span class="wsa">pe</span>rforming an erase <span class="ws8">ope</span>ration in the <span class="ws5">se</span>ctor. This feature <span class="ws5">c</span>a<span class="_ _1"></span>n be <span class="ws5">use</span>d to change the record status </div><div class="t m0 x1 h4 yc6 ff2 fs2 fc0 sc0 ls0 ws0">of a <span class="ws5">da<span class="ws11">ta </span></span>record without a pre<span class="_ _1"></span>vious <span class="ws7">e</span>rase <span class="ws8">whi</span>ch is frequently used in s<span class="ws11">ome </span>EEPROM emulation </div><div class="t m0 x1 h11 yc7 ff6 fs2 fc0 sc0 ls0 ws0">tec<span class="ws10">hniques. </span>It’s importa<span class="_ _1"></span>nt to remark that it is only available and usable f<span class="wsd">or </span>approved drivers by NXP, </div><div class="t m0 x1 h4 yc8 ff2 fs2 fc0 sc0 ls0 ws0">please <span class="ws8">c</span>onsult the <span class="ws5">R</span>TD <span class="ws8">s</span>oftware for <span class="ws9">S</span>32K3 devices for <span class="wsc">a<span class="_ _1"></span><span class="ws0">vailable FEE driv<span class="_ _2"></span>e<span class="_ _1"></span>rs. </span></span></div><div class="t m0 x1 h4 yc9 ff2 fs2 fc0 sc0 ls0 ws0">Before <span class="ws5">a p</span>rogram operations occurs the <span class="ws5">se</span>ctor that <span class="wsf">c</span>ontains the <span class="ws5">spe</span>cifie<span class="_ _1"></span><span class="wsb">d <span class="ws0">address must be unlocke</span>d. <span class="ws0">If <span class="ws9">a </span></span></span></div><div class="t m0 x1 h4 yca ff2 fs2 fc0 sc0 ls0 ws0">locked sector or super sector is attempted to be <span class="ws5">pr</span>ogrammed, program operation will <span class="wsa">fa</span>il <span class="wsa">a</span>nd a<span class="_ _1"></span>n error </div><div class="t m0 x1 h4 ycb ff2 fs2 fc0 sc0 ls0 ws0">will <span class="wsa">be <span class="ws5">re</span></span>ported in the <span class="ws5">M</span>CRS[PEP] bit. </div><div class="t m0 x1 h4 ycc ff2 fs2 fc0 sc0 ls0 ws0">The <span class="wsc">flow <span class="ws8">diagram for <span class="ws5">the <span class="ws11">program operation is </span></span></span></span>explained in the<span class="ws17"> </span><span class="ff7 fc3">Figure 1</span>.<span class="ws18"> </span></div><div class="t m0 x48 hf y3b ff1 fs5 fc0 sc0 ls0 ws0">S32K3 <span class="ws2">Memories </span>Guide, <span class="_ _2"></span>Rev. 0, <span class="ffc">11</span>/2021 </div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/bg5.jpg"><div class="t m0 x3c he y3a ff1 fs6 fc0 sc0 ls0 ws0">Flash memory<span class="_ _1"></span> </div><div class="t m0 x1 h10 y79 ff3 fs6 fc2 sc0 ls0 ws0">NXP Semiconduc<span class="_ _1"></span>tors <span class="_ _a"> </span>5 </div><div class="t m0 x33 h12 ycd ff3 fs7 fc0 sc0 ls0 ws0">Figur<span class="ws19">e </span>1. <span class="_ _e"> </span><span class="ff1">Program sequence flow <span class="ws1a">d<span class="_ _2"></span></span>iagram </span></div><div class="t m0 x1 h28 yce ff3 fsa fc0 sc0 ls0 ws0">3.3. </div><div class="t m0 x4a h29 ycf ff1 fsa fc0 sc0 ls0 ws0">Erase </div><div class="t m0 x1 h4 yd0 ff2 fs2 fc0 sc0 ls0 ws0">The <span class="wsc">e</span>rase <span class="ws8">ope</span>ration is the proce<span class="_ _1"></span>ss to se<span class="wsf">t </span>all <span class="wsa">bit</span>s from a sector or block to 1. <span class="wsb">The <span class="_ _1"></span><span class="wsc">mi<span class="ws0">nimum erase <span class="ws8">size <span class="ws16">c</span></span>an </span></span></span></div><div class="t m0 x1 h4 yd1 ff2 fs2 fc0 sc0 ls0 ws0">be <span class="ws5">pe</span>rformed in a sec<span class="ws10">tor, </span>where a <span class="ws5">se<span class="_ _1"></span><span class="ws0">ctor size <span class="ws1b">is </span>8 KB. To erase a <span class="ws5">se</span>ctor or block it must be unlocked </span></span></div><div class="t m0 x1 h4 yd2 ff2 fs2 fc0 sc0 ls0 ws0">previously to the erase <span class="ws5">o</span>peration. The erase <span class="ws5">proc</span>ess also clean the ECC <span class="ws7">bit</span>s. </div><div class="t m0 x1 h4 yd3 ff2 fs2 fc0 sc0 ls0 ws0">The following flow diagram show the <span class="ws5">erase <span class="ws8">sequence. </span></span></div><div class="t m0 x9 hf yaa ff1 fs5 fc0 sc0 ls0 ws0">S32K3 <span class="ws2">Memories </span>Guide, <span class="_ _2"></span>Rev. <span class="ws2">0, </span><span class="ffd">11</span>/2021 </div><div class="c x4b yd4 w37 h2a"><div class="t m0 x2c h10 y88 ff3 fs6 fc5 sc0 ls0 ws0">This is the Ma<span class="_ _1"></span>ster that start a<span class="_ _1"></span> Progra<span class="_ _1"></span>m </div><div class="t m0 x2c h10 yd5 ff3 fs6 fc5 sc0 ls0 ws0"><span class="fc6 sc0">o</span><span class="fc6 sc0">p</span><span class="fc6 sc0">e</span><span class="fc6 sc0">r</span><span class="fc6 sc0">a</span><span class="fc6 sc0">t</span><span class="fc6 sc0">ion</span><span class="fc6 sc0">.</span></div></div><div class="c x4b y7d w37 h2b"><div class="t m0 x2c h10 yd6 ff3 fs6 fc5 sc0 ls0 ws0">The address to<span class="_ _1"></span> be programed.<span class="_ _1"></span> It repr<span class="_ _1"></span>esent </div><div class="t m0 x2c h10 yd7 ff3 fs6 fc5 sc0 ls0 ws0">the start addre<span class="_ _1"></span>ss when man<span class="_ _1"></span>y data have bee<span class="_ _1"></span>n </div><div class="t m0 x2c h10 yd8 ff3 fs6 fc5 sc0 ls0 ws0">programmed in a <span class="_ _1"></span>single proce<span class="_ _1"></span>ss. </div></div><div class="c x4c yd9 w38 h2c"><div class="t m0 x2c h10 yda ff3 fs6 fc5 sc0 ls0 ws0">DATA contains the<span class="_ _1"></span> data to be<span class="_ _1"></span> programmed<span class="_ _1"></span>. A </div><div class="t m0 x2c h10 ydb ff3 fs6 fc5 sc0 ls0 ws0">write to Data regi<span class="_ _1"></span>ster is refer<span class="_ _1"></span>red to as </div><div class="t m0 x2c h10 ydc ff3 fs6 fc5 sc0 ls0 ws0">interlock write. It<span class="_ _1"></span> must be perfor<span class="_ _1"></span>med before<span class="_ _1"></span> </div><div class="t m0 x2c h10 ydd ff3 fs6 fc5 sc0 ls0 ws0">MCR[PGM] is <span class="_ _1"></span>set to 1. </div></div><div class="c x4c yb0 w38 h2d"><div class="t m0 x2c h10 yde ff3 fs6 fc5 sc0 ls0 ws0">A program seque<span class="_ _1"></span>nce will be<span class="_ _1"></span> executed<span class="_ _1"></span> into the </div><div class="t m0 x2c h10 ydf ff3 fs6 fc5 sc0 ls0 ws0">Flash memory. </div></div><div class="c x4d ye0 w38 h2e"><div class="t m0 x2c h10 ye1 ff3 fs6 fc5 sc0 ls0 ws0">The Enable High<span class="_ _1"></span> Voltage (<span class="_ _1"></span>EHV) bit is turne<span class="_ _1"></span>d </div><div class="t m0 x2c h10 ye2 ff3 fs6 fc5 sc0 ls0 ws0">on to perform the<span class="_ _1"></span> program ope<span class="_ _1"></span>ration. If EH<span class="_ _1"></span>V </div><div class="t m0 x2c h10 ye3 ff3 fs6 fc5 sc0 ls0 ws0">is cleared before<span class="_ _1"></span> DONE bit goe<span class="_ _1"></span>s High then </div><div class="t m0 x2c h10 ye4 ff3 fs6 fc5 sc0 ls0 ws0">the operation i<span class="_ _1"></span>s aborted and<span class="_ _1"></span> PEG is clea<span class="_ _1"></span>red </div><div class="t m0 x2c h10 y5c ff3 fs6 fc5 sc0 ls0 ws0">indicating a failed pr<span class="_ _1"></span>ogram. </div></div><div class="c x4d ye5 w38 h2f"><div class="t m0 x2c h10 yde ff3 fs6 fc5 sc0 ls0 ws0">MCRS[DONE] is<span class="_ _1"></span> 0 when a pr<span class="_ _1"></span>ogram or erase<span class="_ _1"></span> </div><div class="t m0 x2c h10 ydf ff3 fs6 fc5 sc0 ls0 ws0">operation is on e<span class="_ _1"></span>xecution. </div></div><div class="c x4c ye6 w38 h30"><div class="t m0 x2c h10 ye7 ff3 fs6 fc5 sc0 ls0 ws0">When the MCRS[<span class="_ _1"></span>PEG] is se<span class="_ _1"></span>t to 1 then<span class="_ _1"></span> it </div><div class="t m0 x2c h10 ye8 ff3 fs6 fc5 sc0 ls0 ws0">indicates that the pr<span class="_ _1"></span>ogram pr<span class="_ _1"></span>ocess was </div><div class="t m0 x2c h10 ye9 ff3 fs6 fc5 sc0 ls0 ws0">successful. In<span class="_ _1"></span> other case its<span class="_ _1"></span> value w<span class="_ _1"></span>ill be 0, </div><div class="t m0 x2c h10 yea ff3 fs6 fc5 sc0 ls0 ws0">indicating that <span class="_ _1"></span>the sequence failed<span class="_ _1"></span>. </div></div><div class="c x4c yeb w38 h31"><div class="t m0 x2c h10 yec ff3 fs6 fc5 sc0 ls0 ws0">The EHV mus<span class="_ _1"></span>t be turned of<span class="_ _1"></span>f when the </div><div class="t m0 x2c h10 y72 ff3 fs6 fc5 sc0 ls0 ws0">program oper<span class="_ _1"></span>ation has finished. </div></div><div class="c x4c yed w38 h32"><div class="t m0 x2c h10 yee ff3 fs6 fc5 sc0 ls0 ws0">The program sequen<span class="_ _1"></span>ce is fini<span class="_ _1"></span>shed. The <span class="_ _1"></span>flash </div><div class="t m0 x2c h10 y8a ff3 fs6 fc5 sc0 ls0 ws0">memory has per<span class="_ _1"></span>formed a pro<span class="_ _1"></span>gram sequence<span class="_ _1"></span> </div><div class="t m0 x2c h10 yef ff3 fs6 fc5 sc0 ls0 ws0">and another ope<span class="_ _1"></span>ration can be <span class="_ _1"></span>initiated after<span class="_ _1"></span> it. </div></div><div class="c x4e yf0 w39 h33"><div class="t m0 x15 h10 yf1 ff3 fs6 fc0 sc0 ls0 ws0">PGM Start do<span class="_ _1"></span>main ID=1</div></div><div class="c x4f yf2 w3a h34"><div class="t m0 x7 h10 y4f ff3 fs6 fc0 sc0 ls0 ws0">Write the addr<span class="_ _1"></span>ess to the PFC<span class="_ _1"></span>PGM_PEADR<span class="_ _1"></span>_L register</div></div><div class="c x50 yf3 w3b h35"><div class="t m0 x2d h10 yf4 ff3 fs6 fc0 sc0 ls0 ws0">Wait until the </div><div class="t m0 x27 h10 yf5 ff3 fs6 fc0 sc0 ls0 ws0">MCRS[DONE] </div><div class="t m0 x8 h10 yf6 ff3 fs6 fc0 sc0 ls0 ws0">goes high </div></div><div class="c x4f yf7 w3a h36"><div class="t m0 x2e h10 y61 ff3 fs6 fc0 sc0 ls0 ws0">Data to be prog<span class="_ _1"></span>rammed must be<span class="_ _1"></span> wr<span class="_ _1"></span>itten in the </div><div class="t m0 x7 h37 y5a ff3 fs6 fc0 sc0 ls9 ws0">appropriate Program <span class="_ _2"></span>DATA<span class="_ _1"></span>x [Data0 <span class="ffe ls0">–<span class="ff3"> Data31] register</span></span></div></div><div class="c x34 yf8 w3c h38"><div class="t m0 x51 h10 y21 ff3 fs6 fc0 sc0 ls0 ws0">Change the value<span class="_ _1"></span> in the MCR<span class="_ _1"></span>[PGM] bit <span class="_ _1"></span>from 0 to 1</div></div><div class="c x4f yf9 w3a h36"><div class="t m0 x14 h10 y4d ff3 fs6 fc0 sc0 ls0 ws0">Write a logic 1 <span class="_ _1"></span>to the MCR[EHV<span class="_ _1"></span>] bit to start<span class="_ _1"></span> the internal </div><div class="t m0 x49 h10 yfa ff3 fs6 fc0 sc0 ls0 ws0">program sequen<span class="_ _1"></span>ce</div></div><div class="c x4f yfb w3a h39"><div class="t m0 x22 h10 y69 ff3 fs6 fc0 sc0 ls0 ws0">Confirm MCRS[PEG<span class="_ _1"></span>] = 1</div></div><div class="c x4f yfc w3a h38"><div class="t m0 x52 h10 y21 ff3 fs6 fc0 sc0 ls0 ws0">Write a logic 0 <span class="_ _1"></span>to the MCR[EHV<span class="_ _1"></span>] bit</div></div><div class="c x4f yfd w3a ha"><div class="t m0 x27 h10 y4d ff3 fs6 fc0 sc0 ls0 ws0">Write a logic 0 <span class="_ _1"></span>to the MCR[PG<span class="_ _1"></span>M] bit to ter<span class="_ _1"></span>minate the </div><div class="t m0 x49 h10 yfa ff3 fs6 fc0 sc0 ls0 ws0">program sequen<span class="_ _1"></span>ce</div></div><div class="c x4e yfe w3d h3a"><div class="t m0 x32 h10 yff ff3 fs6 fc0 sc0 ls0 ws0">PGM End</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>