S32K3 memory

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汽车级芯片S32k3 memory开发指导
AN13388_S32K3 Memories Guide.7z
  • AN13388_S32K3 Memories Guide.pdf
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/627f6001ebb030486d20631e/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">S32K3 Memories Guide </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">1.<span class="_ _0"> </span><span class="ls0">Introduction</span></div><div class="t m0 x1 h4 y3 ff2 fs2 fc0 sc0 ls0 ws0">The purpose of this application note is to provide a </div><div class="t m0 x1 h4 y4 ff2 fs2 fc0 sc0 ls0 ws0">guideline to the readers about the memory features </div><div class="t m0 x1 h4 y5 ff2 fs2 fc0 sc0 ls0 ws0">included in the S32K3 Product Family. This document </div><div class="t m0 x1 h4 y6 ff2 fs2 fc0 sc0 ls0 ws0">details the available functions and best practice<span class="_ _1"></span>s for </div><div class="t m0 x1 h4 y7 ff2 fs2 fc0 sc0 ls0 ws0">running applications considering performance </div><div class="t m0 x1 h4 y8 ff2 fs2 fc0 sc0 ls0 ws0">improvements. </div><div class="t m0 x1 h4 y9 ff2 fs2 fc0 sc0 ls0 ws0">You can find four kinds of memories inside S32K3 </div><div class="t m0 x1 h4 ya ff2 fs2 fc0 sc0 ls0 ws0">Product Family, the Flash memory, the SRAM, the </div><div class="t m0 x1 h4 yb ff2 fs2 fc0 sc0 ls0 ws0">Tightly Coupled Memory (TCM) and the Cache </div><div class="t m0 x1 h4 yc ff2 fs2 fc0 sc0 ls0 ws0">Memory. The S32K3 Product Family also have some </div><div class="t m0 x1 h4 yd ff2 fs2 fc0 sc0 ls0 ws0">modules with dedicated memory such like EMAC and </div><div class="t m0 x1 h4 ye ff2 fs2 fc0 sc0 ls0 ws0">CAN. This document will mainly focus on Flash </div><div class="t m0 x1 h4 yf ff2 fs2 fc0 sc0 ls0 ws0">Memory, TCM and SRAM. </div><div class="t m0 x1 h4 y10 ff2 fs2 fc0 sc0 ls0 ws0">The Flash memory is dedicated for program code and </div><div class="t m0 x1 h4 y11 ff2 fs2 fc0 sc0 ls0 ws0">store data. Also, all devices in the family has a UTEST </div><div class="t m0 x1 h4 y12 ff2 fs2 fc0 sc0 ls0 ws0">sector of 8 KB for store important configurations or to </div><div class="t m0 x1 h4 y13 ff2 fs2 fc0 sc0 ls0 ws0">reserve information for the application. The S32K3 </div><div class="t m0 x1 h4 y14 ff2 fs2 fc0 sc0 ls0 ws0">Product Family has devices from 512 KB to 8 MB of </div><div class="t m0 x1 h4 y15 ff2 fs2 fc0 sc0 ls0 ws0">Flash program memory. </div><div class="t m0 x1 h4 y16 ff2 fs2 fc0 sc0 ls0 ws0">The RAM is integrated by the SRAM memory and the </div><div class="t m0 x1 h4 y17 ff2 fs2 fc0 sc0 ls0 ws0">TCM. Part of the SRAM memory is available in standby </div><div class="t m0 x1 h4 y18 ff2 fs2 fc0 sc0 ls0 ws0">mode. This means that the content of this memory are </div><div class="t m0 x1 h4 y19 ff2 fs2 fc0 sc0 ls0 ws0">retained after setting the MCU in standby mode. The </div><div class="t m0 x1 h4 y1a ff2 fs2 fc0 sc0 ls0 ws0">S32K3 product family leverages the TCM feature of </div><div class="t m0 x1 h4 y1b ff2 fs2 fc0 sc0 ls0 ws0">ARM Cortex M7 architecture, whose main purpose is to </div><div class="t m0 x1 h4 y1c ff2 fs2 fc0 sc0 ls0 ws0">provide a deterministic access time to the c<span class="_ _1"></span>ores to some </div><div class="t m0 x1 h4 y1d ff2 fs2 fc0 sc0 ls0 ws0">important data avoiding any delay in the acce<span class="_ _1"></span>ss. This </div><div class="t m0 x1 h4 y1e ff2 fs2 fc0 sc0 ls0 ws0">feature can be exploited in Real Time Operating </div><div class="t m0 x1 h4 y1f ff2 fs2 fc0 sc0 ls0 ws0">Systems. </div><div class="c x1 y20 w2 h5"><div class="t m0 x0 h6 y21 ff1 fs3 fc0 sc0 ls0 ws0">NXP Semiconductors<span class="_ _2"></span> </div></div><div class="c x1 y22 w2 h7"><div class="t m0 x0 h8 y23 ff3 fs3 fc0 sc0 ls0 ws0">Application Notes<span class="_ _2"></span> </div></div><div class="t m0 x2 h9 y24 ff3 fs2 fc0 sc0 ls0 ws1">Document <span class="ws0">Number:AN13388 </span></div><div class="t m0 x3 h9 y25 ff3 fs2 fc0 sc0 ls0 ws0">Rev. 0,<span class="ff4"> 11</span>/2021</div><div class="c x4 y26 w3 ha"><div class="t m0 x5 hb y27 ff1 fs4 fc0 sc0 ls0 ws0">Contents<span class="_ _2"></span> </div></div><div class="c x6 y28 w4 hc"><div class="t m0 x7 hd y29 ff2 fs5 fc1 sc0 ls2 ws0">1.<span class="_ _3"> </span><span class="ls0">Introduction <span class="_ _4"></span><span class="ls3">........................................................................<span class="ls0"> <span class="_ _5"></span>1</span></span></span></div><div class="t m0 x7 hd y2a ff2 fs5 fc1 sc0 ls2 ws0">2.<span class="_ _3"> </span><span class="ls0">Features <span class="_ _6"></span><span class="ls3">..............................................................................<span class="ls0"> <span class="_ _5"></span>2</span></span></span></div><div class="t m0 x7 hd y2b ff2 fs5 fc1 sc0 ls2 ws0">3.<span class="_ _3"> </span><span class="ls0">Flash memory <span class="ls3">....................................................................</span> <span class="_ _5"></span>3</span></div><div class="t m0 x8 hd y2c ff2 fs5 fc1 sc0 ls0 ws0">3.1.<span class="_ _7"> </span>Read <span class="_ _8"></span><span class="ls3">........................................................................<span class="ls0"> <span class="_ _5"></span>4</span></span></div><div class="t m0 x8 hd y2d ff2 fs5 fc1 sc0 ls0 ws0">3.2.<span class="_ _7"> </span>Write or Program <span class="_ _5"></span><span class="ls3">....................................................<span class="ls0"> <span class="_ _5"></span>4</span></span></div><div class="t m0 x8 hd y2e ff2 fs5 fc1 sc0 ls0 ws0">3.3.<span class="_ _7"> </span>Erase <span class="_ _5"></span><span class="ls3">.......................................................................<span class="ls0"> <span class="_ _1"></span>5</span></span></div><div class="t m0 x8 hd y2f ff2 fs5 fc1 sc0 ls0 ws0">3.4.<span class="_ _7"> </span>Locking and unlocking sector or super sector <span class="_ _6"></span><span class="ls3">.........<span class="ls0"> <span class="_ _1"></span>8</span></span></div><div class="t m0 x8 hd y30 ff2 fs5 fc1 sc0 ls0 ws0">3.5.<span class="_ _7"> </span>UTEST sector <span class="_ _1"></span><span class="ls3">.........................................................<span class="ls0"> <span class="_ _5"></span>9</span></span></div><div class="t m0 x7 hd y31 ff2 fs5 fc1 sc0 ls2 ws0">4.<span class="_ _3"> </span><span class="ls0">Tightly Coupled Memory <span class="_ _4"></span><span class="ls3">.................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">10</span></span></span></span></div><div class="t m0 x7 hd y32 ff2 fs5 fc1 sc0 ls2 ws0">5.<span class="_ _3"> </span><span class="ls0">SRAM <span class="_ _8"></span><span class="ls3">..............................................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">12</span></span></span></span></div><div class="t m0 x8 hd y33 ff2 fs5 fc1 sc0 ls0 ws0">5.1.<span class="_ _7"> </span>Read <span class="_ _8"></span><span class="ls3">......................................................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">14</span></span></span></div><div class="t m0 x8 hd y34 ff2 fs5 fc1 sc0 ls0 ws0">5.2.<span class="_ _7"> </span>Write <span class="_ _9"></span><span class="ls3">.....................................................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">14</span></span></span></div><div class="t m0 x7 hd y35 ff2 fs5 fc1 sc0 ls2 ws0">6.<span class="_ _3"> </span><span class="ls0">Use Cases <span class="_ _6"></span><span class="ls3">.........................................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">15</span></span></span></span></div><div class="t m0 x8 hd y36 ff2 fs5 fc1 sc0 ls0 ws0">6.1.<span class="_ _7"> </span>Flash vs TCM vs SRAM <span class="_ _6"></span><span class="ls3">.......................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">15</span></span></span></div><div class="t m0 x8 hd y37 ff2 fs5 fc1 sc0 ls0 ws0">6.2.<span class="_ _7"> </span>SRAM standby <span class="_ _4"></span><span class="ls3">......................................................<span class="ls0"> <span class="_ _1"></span><span class="ls2">21</span></span></span></div><div class="t m0 x7 hd y38 ff2 fs5 fc1 sc0 ls2 ws0">7.<span class="_ _3"> </span><span class="ls0">SW recommendations and conclusions <span class="_ _6"></span><span class="ls3">............................<span class="ls0"> <span class="_ _1"></span><span class="ls2">26</span></span></span></span></div><div class="t m0 x7 hd y39 ff2 fs5 fc1 sc0 ls2 ws0">8.<span class="_ _3"> </span><span class="ls0">References <span class="_ _4"></span><span class="ls3">........................................................................<span class="ls0"> <span class="_ _5"></span><span class="ls2">26</span></span></span></span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return 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