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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628329339b6e2b6d55d5bf9e/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y3 ff2 fs1 fc1 sc0 ls1 ws0">UM1021<span class="_ _0"></span>1</div><div class="t m0 x2 h4 y4 ff2 fs2 fc1 sc0 ls2 ws1">LPC2364/6/8/78 User manual</div><div class="t m0 x2 h5 y5 ff2 fs3 fc1 sc0 ls3 ws2">Rev<span class="_ _1"></span>. 01 — 6 October 2006<span class="_ _2"> </span>User manual</div><div class="t m0 x1 h6 y6 ff2 fs4 fc1 sc0 ls4 ws3">Documen<span class="_ _3"></span>t informat<span class="_ _3"></span>ion</div><div class="t m0 x3 h6 y7 ff2 fs4 fc2 sc0 ls5 ws0">Info<span class="_ _4"> </span><span class="ls6">Content</span></div><div class="t m0 x3 h6 y8 ff2 fs4 fc2 sc0 ls7 ws0">Keywords<span class="_ _5"> </span><span class="ff1 ls8 ws4">LPC2300, LPC2364, LPC2366, <span class="_ _6"></span>LPC2368, LPC2378, ARM, <span class="_ _6"></span>ARM7, 32-bit, </span></div><div class="t m0 x4 h7 y9 ff1 fs4 fc2 sc0 ls9 ws5">USB, Ethernet, CAN, I2S, Microcontroller</div><div class="t m0 x3 h6 ya ff2 fs4 fc2 sc0 lsa ws0">Abstract<span class="_ _7"> </span><span class="ff1 lsb ws6">An initial<span class="_ _6"></span> LPC2364/6/8<span class="_ _6"></span>/78 User manual<span class="_ _6"></span> revision</span></div></div><div class="pi" data-data='{"ctm":[1.610738,0.000000,0.000000,1.610738,-12.885906,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628329339b6e2b6d55d5bf9e/bg2.jpg"><div class="t m1 x5 h8 yb ff1 fs5 fc2 sc0 lsc ws0">UM1021<span class="_ _3"></span>1_1<span class="_ _8"> </span><span class="lsd ws7">© Koninklijke Ph<span class="_ _6"></span>ilips Electronics <span class="_ _6"></span>N.V<span class="_ _3"></span>. 2006. All rights reserved.</span></div><div class="t m1 x5 h9 yc ff2 fs6 fc1 sc0 lse ws8">User manual <span class="_ _9"> </span>Rev<span class="_ _a"></span>. 01 — 6 October 2006 <span class="_ _b"> </span>2 of 612</div><div class="t m1 x5 ha yd ff2 fs7 fc1 sc0 lsf ws9">Cont<span class="_ _a"></span>act information</div><div class="t m1 x5 hb ye ff1 fs8 fc2 sc0 ls10 wsa">For additional information, please visit: <span class="ff2 ls11 ws0">http://www<span class="_ _a"></span>.semiconductors.philip<span class="_ _a"></span>s.com</span></div><div class="t m1 x5 hb yf ff1 fs8 fc2 sc0 ls12 wsb">For sales of<span class="_ _a"></span>fice addresses, please send an email to: <span class="ff2 ls13 ws0">sales.addresses@www<span class="_ _a"></span>.sem<span class="ls14">iconductors.philip<span class="_ _a"></span>s.com</span></span></div><div class="t m1 x5 hc y10 ff2 fs9 fc1 sc0 ls15 wsc">Philip<span class="_ _a"></span>s Semiconductors</div><div class="t m1 x6 hd y11 ff2 fsa fc1 sc0 ls16 ws0">UM1021<span class="_ _1"></span>1</div><div class="t m1 x7 hb y12 ff2 fs8 fc1 sc0 ls17 wsd">LPC23xx User manual</div><div class="t m1 x1 h2 y13 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m1 x5 h6 y14 ff2 fs4 fc1 sc0 ls18 ws0">Revision hi<span class="_ _3"></span>story</div><div class="t m1 x8 h6 y15 ff2 fs4 fc2 sc0 ls19 ws0">Rev<span class="_ _c"> </span><span class="ls1a">Date<span class="_ _d"> </span><span class="ls1b">Description</span></span></div><div class="t m1 x8 h7 y16 ff1 fs4 fc2 sc0 ls1c wse">01<span class="_ _e"> </span>20061006<span class="_ _f"> </span>Changes made to 20061002 editi<span class="_ _6"></span>on:</div><div class="t m1 x9 hc y17 ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs4 lsa wsf">Pad structure details added in <span class="fc3 ls1d ws10">T<span class="_ _1"></span>able 8–79 “<span class="ls1e ws11">LPC2364/6/8<span class="_ _6"></span> pi<span class="ws12">n description<span class="ls0 ws0">”<span class="fc2 ls1f ws13"> and </span><span class="ls20">Ta<span class="_ _11"></span>b<span class="_ _11"></span>l<span class="_ _11"></span>e<span class="_ _12"></span> </span></span></span></span></span></span></div><div class="t m1 xa h7 y18 ff1 fs4 fc3 sc0 ls1d ws10">8–80 “<span class="ls21 ws14">LPC2378 pi<span class="ls22 ws15">n de<span class="_ _6"></span>scription<span class="ls0 ws0">”</span></span></span></div><div class="t m1 x9 hc y19 ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs4 ls9 ws16">order of the “On-Ch<span class="_ _6"></span>ip RAM“ elements adjusted in <span class="fc3 ls23 ws17">T<span class="_ _1"></span>able 2–3 “<span class="_ _6"></span><span class="ls1f ws0">LPC<span class="ls1d">2300 <span class="ls24">me<span class="ls25">mory <span class="ls26">usage<span class="ls0">”</span></span></span></span></span></span></span></span></div><div class="t m1 xb h7 y1a ff1 fs4 fc2 sc0 ls21 ws18">20061002<span class="_ _f"> </span>Preliminary LPC234/6/8<span class="_ _6"></span>/78 User manual</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.610738,0.000000,0.000000,1.610738,-12.885906,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628329339b6e2b6d55d5bf9e/bg3.jpg"><div class="t m1 x5 h8 yb ff1 fs5 fc2 sc0 lsc ws0">UM1021<span class="_ _a"></span>1_<span class="_ _6"></span>1<span class="_ _8"> </span><span class="lsd ws7">© Koninklijke Ph<span class="_ _6"></span>ilips Electronics <span class="_ _6"></span>N.V<span class="_ _a"></span>. 2006. All ri<span class="_ _6"></span>ghts reserved.</span></div><div class="t m1 x5 h9 yc ff2 fs6 fc1 sc0 lse ws8">User manual <span class="_ _9"> </span>Rev<span class="_ _a"></span>. 01 — 6 October 2006 <span class="_ _b"> </span>3 of 612</div><div class="t m1 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m1 x5 ha y1b ff2 fs7 fc1 sc0 ls27 ws0">1.<span class="_ _13"> </span>Introduction</div><div class="t m1 x1 he y1c ff1 fs8 fc2 sc0 ls28 ws19">LPC2364/6/8/78 is an ARM-based micr<span class="_ _3"></span>ocontro<span class="ls17 ws1a">ller for applications<span class="ls29 ws1b"> requiring serial </span></span></div><div class="t m1 x1 he y1d ff1 fs8 fc2 sc0 ls2a ws1c">communicat<span class="_ _6"></span>ions for a va<span class="_ _6"></span>riety of purp<span class="_ _6"></span>oses. These m<span class="_ _6"></span>icrocontrolle<span class="_ _6"></span>rs incorpor<span class="_ _6"></span>ate a 10/100<span class="_ _6"></span> </div><div class="t m1 x1 he y1e ff1 fs8 fc2 sc0 ls28 ws19">Ethernet MAC, USB 2.0 Full S<span class="_ _a"></span>peed interface,<span class="ws1d"> fo<span class="_ _a"></span>ur <span class="_ _6"></span>UART<span class="_ _0"></span>s, two CAN channels, an SPI </span></div><div class="t m1 x1 he y1f ff1 fs8 fc2 sc0 ls10 ws1e">interface, two Sync<span class="ls2b ws1f">hronous Serial Ports (SSP), three I</span></div><div class="t m1 xc hf y20 ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 xd he y21 ff1 fs8 fc2 sc0 ls2c ws20">C interfaces, an I2S interface, and </div><div class="t m1 x1 he y22 ff1 fs8 fc2 sc0 ls2d ws1d">a MiniBus (LPC2378 only: 8-bit dat<span class="_ _a"></span>a/16-bit address parallel bus).</div><div class="t m1 x1 hb y23 ff2 fs8 fc2 sc0 ls12 ws0">Import<span class="_ _a"></span>ant:<span class="ff1 ls2e ws21"> T<span class="_ _1"></span>erm “LPC2300“ in the following text <span class="ls2f ws22">will be used as a generic name for all </span></span></div><div class="t m1 x1 he y24 ff1 fs8 fc2 sc0 ls11 ws23">four part<span class="_ _a"></span>s covered with this user manual: <span class="ls28 ws19">LPC2364, LPC2366, LPC2368, and LPC2378. </span></div><div class="t m1 x1 he y25 ff1 fs8 fc2 sc0 ls2f ws22">Only when needed, a specific<span class="ls30 ws24"> device name will be used to<span class="ws1a"> single out one of them.</span></span></div><div class="t m1 x5 ha y26 ff2 fs7 fc1 sc0 ls31 ws0">2.<span class="_ _13"> </span>Features</div><div class="t m1 xe hc y27 ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls32 ws25">ARM7TDMI-S processor<span class="_ _a"></span>, running at up to 72<span class="_"> </span>MHz.</span></div><div class="t m1 xe hc y28 ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls33 ws26">Up to 512<span class="_"> </span>kB on-chip Flash Progra<span class="_ _3"></span>m Memory<span class="_ _6"></span> with In-System Prog<span class="_ _a"></span>ramming (ISP) and </span></div><div class="t m1 xf he y29 ff4 fs8 fc2 sc0 ls34 ws27">In-Application Progr<span class="_ _3"></span>amming (IAP) <span class="ls35 ws28">capabilities. Single Flash se<span class="ls36 ws29">ctor or full chip erase in </span></span></div><div class="t m1 xf he y2a ff4 fs8 fc2 sc0 ls2a ws2a">400 ms and 256 bytes programming in 1 ms. Flash program memo<span class="_ _6"></span>ry is on th<span class="_ _6"></span>e ARM </div><div class="t m1 xf he y2b ff4 fs8 fc2 sc0 ls37 ws2b">local b<span class="_ _3"></span>us f<span class="_ _a"></span>or high perf<span class="_ _a"></span>or<span class="_ _6"></span>mance CPU access.</div><div class="t m1 xe hc y2c ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls28 ws2c">Up to 32<span class="_"> </span>kB of SRAM on the ARM local bus f<span class="_ _a"></span>or high perf<span class="_ _a"></span>or<span class="_ _6"></span>mance CPU access.</span></div><div class="t m1 xe hc y2d ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls33 ws2d">16<span class="_"> </span>kB Static RAM for Ethe<span class="_ _a"></span>r<span class="_ _6"></span>net interf<span class="_ _3"></span>ace. Can also be used a<span class="_ _3"></span>s general purpose SRAM.</span></div><div class="t m1 xe hc y2e ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls38 ws2e">8<span class="_"> </span>kB Static RAM f<span class="_ _a"></span>or USB interfa<span class="_ _3"></span>ce. Can also be<span class="_ _a"></span> <span class="_ _6"></span>used as genera<span class="_ _a"></span>l pur<span class="_ _6"></span>pose SRAM.</span></div><div class="t m1 xe hc y2f ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls39 ws2f">Dual AHB system that pro<span class="_ _a"></span>vides for simult<span class="_ _3"></span>aneous Ethernet DMA, USB DMA, and </span></div><div class="t m1 xf he y30 ff4 fs8 fc2 sc0 ls38 ws2e">progr<span class="_ _a"></span>am ex<span class="_ _a"></span>ecution from on-chip Flash with no conte<span class="_ _3"></span>ntion betwee<span class="_ _a"></span>n those functions. A </div><div class="t m1 xf he y31 ff4 fs8 fc2 sc0 ls28 ws2c">bus bridge allo<span class="_ _3"></span>ws the Ethernet DMA to access the other AHB subsystem.</div><div class="t m1 xe hc y32 ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls3a ws30">External memor<span class="_ _6"></span>y controller that suppor<span class="_ _6"></span>ts st<span class="ls2d ws31">atic de<span class="_ _a"></span>vices such as Flash and SRAM. An </span></span></div><div class="t m1 xf he y33 ff4 fs8 fc2 sc0 ls2d ws2c">8-bit data/16-bit<span class="_ _a"></span> <span class="_ _6"></span>address parallel b<span class="_ _a"></span>us is av<span class="_ _a"></span>ailable in LPC2378 only<span class="_ _0"></span>.</div><div class="t m1 xe hc y34 ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls3b ws32">Adv<span class="_ _3"></span>anced V<span class="_ _1"></span>ectored Inte<span class="_ _3"></span>rrupt Controller<span class="_ _1"></span>, suppor<span class="_ _6"></span>ting up to 32 v<span class="_ _3"></span>ectored interrupts<span class="_ _a"></span>.</span></div><div class="t m1 xe hc y35 ff3 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff4 fs8 ls2c ws33">General Purpose AHB DMA controller (GPDMA) <span class="ls30 ws34">that can be used with the SSP serial </span></span></div><div class="t m1 xf he y36 ff4 fs8 fc2 sc0 ls37 ws35">interf<span class="_ _a"></span>aces, the I2S port, and the SD/MMC card port, as well as f<span class="_ _3"></span>or memory-to-memor<span class="_ _6"></span>y </div><div class="t m1 xf he y37 ff4 fs8 fc2 sc0 ls3c ws0">transfers<span class="_ _3"></span>.</div><div class="t m1 xe hc y38 ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls3d ws36">Serial Interfaces:</span></div><div class="t m1 xf hb y39 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls3e ws37">Ethernet MAC with associa<span class="_ _3"></span>ted DMA contro<span class="ls11 ws23">ller<span class="_ _1"></span>. These functions reside on an </span></span></div><div class="t m1 x10 he y3a ff1 fs8 fc2 sc0 ls11 ws38">independent AHB bus.</div><div class="t m1 xf hb y3b ff3 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff4 ls28 ws2c">USB 2.0 De<span class="_ _a"></span>vice with on-chip PHY and associated DMA controller<span class="_ _1"></span>.</span></div><div class="t m1 xf hb y3c ff3 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff4 ls3f ws39">F<span class="_ _a"></span>our U<span class="_ _a"></span>ARTs wit<span class="_ _3"></span>h fracti<span class="_ _3"></span>onal baud r<span class="_ _a"></span>ate generation<span class="_ _3"></span>, one with mo<span class="_ _3"></span>dem control I<span class="_ _a"></span>/<span class="_ _6"></span>O<span class="_ _a"></span>, one </span></div><div class="t m1 x10 he y3d ff4 fs8 fc2 sc0 ls40 ws3a">with IrD<span class="_ _a"></span>A suppor<span class="_ _12"></span>t, all with FIFO<span class="_ _a"></span><span class="ls41 ws22">. These reside on the APB bus.</span></div><div class="t m1 xf hb y3e ff3 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff4 ls42 ws3b">T<span class="_ _0"></span>wo CAN channels with Acceptance Filt<span class="ls2c ws3c">er/FullCAN mode reside on the APB b<span class="_ _a"></span>u<span class="_ _6"></span>s.</span></span></div><div class="t m1 xf hb y3f ff3 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff4 ls41 ws3d">SPI controller<span class="_ _a"></span>, residing on the APB b<span class="_ _a"></span>us.</span></div><div class="t m1 xf hb y40 ff3 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff4 ls30 ws3e">T<span class="_ _0"></span>wo SSP controllers with FIFO <span class="ls2e ws3f">and multi-protocol capabilit<span class="ls41 ws22">ies. One is an alternate </span></span></span></div><div class="t m1 x10 he y41 ff4 fs8 fc2 sc0 ls42 ws3b">f<span class="_ _a"></span>or the SPI por<span class="_ _6"></span>t<span class="_ _6"></span>, sharing its interr<span class="_ _6"></span>upt an<span class="ls2c wsa">d pins. The SSP controllers can be used </span></div><div class="t m1 x10 he y42 ff4 fs8 fc2 sc0 ls2f ws21">with the GPDMA controller <span class="ls32 ws23">and reside on the APB bus.</span></div><div class="t m1 x2 h3 y3 ff2 fs1 fc1 sc0 ls1 ws0">UM1021<span class="_ _0"></span>1</div><div class="t m1 x2 h4 y4 ff2 fs2 fc1 sc0 ls43 ws40">Chapter<span class="_"> </span>1:<span class="_"> </span>Introductory information</div><div class="t m1 x2 h5 y5 ff2 fs3 fc1 sc0 ls3 ws41">Rev<span class="_ _1"></span>. 01 — 6 October 2006<span class="_ _2"> </span>User manual</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.610738,0.000000,0.000000,1.610738,-12.885906,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628329339b6e2b6d55d5bf9e/bg4.jpg"><div class="t m1 x5 h8 yb ff1 fs5 fc2 sc0 lsc ws0">UM1021<span class="_ _a"></span>1_<span class="_ _6"></span>1<span class="_ _8"> </span><span class="lsd ws7">© Koninklijke Ph<span class="_ _6"></span>ilips Electronics <span class="_ _6"></span>N.V<span class="_ _a"></span>. 2006. All ri<span class="_ _6"></span>ghts reserved.</span></div><div class="t m1 x5 h9 yc ff2 fs6 fc1 sc0 lse ws8">User manual <span class="_ _9"> </span>Rev<span class="_ _a"></span>. 01 — 6 October 2006 <span class="_ _b"> </span>4 of 612</div><div class="t m1 x5 hc y10 ff2 fs9 fc1 sc0 ls15 wsc">Philip<span class="_ _a"></span>s Semiconductors</div><div class="t m1 x6 hd y11 ff2 fsa fc1 sc0 ls16 ws0">UM1021<span class="_ _1"></span>1</div><div class="t m1 x11 hb y12 ff2 fs8 fc1 sc0 ls39 ws42">Chapter 1: LPC2300 Introduc<span class="_ _3"></span>tory information</div><div class="t m1 xf hb y43 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls44 ws43">Three I</span></div><div class="t m1 x12 hf y44 ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 x13 he y43 ff1 fs8 fc2 sc0 ls39 ws42">C Interfaces reside on the APB bu<span class="_ _3"></span>s. The second and thir<span class="_ _3"></span>d I</div><div class="t m1 x14 hf y44 ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 x15 he y43 ff1 fs8 fc2 sc0 ls30 ws24">C interfaces </div><div class="t m1 x10 he y45 ff1 fs8 fc2 sc0 ls45 ws44">are expansion I</div><div class="t m1 x16 hf y46 ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 x17 he y47 ff1 fs8 fc2 sc0 ls12 wsb">Cs with standard po<span class="_ _a"></span>rt pins rather than special open drain I</div><div class="t m1 x18 hf y46 ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 x19 he y47 ff1 fs8 fc2 sc0 ls46 ws45">C pins.</div><div class="t m1 xf hb y48 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1">I</span></div><div class="t m1 x9 hf y49 ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 x1a he y4a ff1 fs8 fc2 sc0 ls2d ws1d">S (Inter-IC Sound) interface fo<span class="_ _a"></span>r digital audio input or output, residing on the APB </div><div class="t m1 x10 he y4b ff1 fs8 fc2 sc0 ls2d ws46">bus. The I</div><div class="t m1 x1b hf y4c ff1 fsb fc2 sc0 ls0 ws0">2</div><div class="t m1 x1c he y4d ff1 fs8 fc2 sc0 ls3a ws47">S interface can be used with the GPDMA.</div><div class="t m1 xe hc y4e ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls17 wsd">Other APB Peripherals:</span></div><div class="t m1 xf hb y4f ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls17 ws1a">Secure Digital (SD) / MultiMediaCa<span class="ls47 ws48">rd (MMC)<span class="_ _6"></span> memory ca<span class="_ _6"></span>rd interfac<span class="_ _6"></span>e.</span></span></div><div class="t m1 xf hb y50 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls38 ws2f">Up to 70 (LPC2364/6/8) or<span class="_ _a"></span> <span class="_ _6"></span>104 (LPC2378) gener<span class="_ _a"></span>al purpose I/O pins.</span></div><div class="t m1 xf hb y51 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls12 wsb">10 bit A/D converter with i<span class="ls39 ws42">nput mu<span class="_ _a"></span>ltiplexing among 6 pins (LPC2364/66/68) or 8 </span></span></div><div class="t m1 x10 he y52 ff1 fs8 fc2 sc0 ls13 ws49">pins LPC2378).</div><div class="t m1 xf hb y53 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls28 ws19">10 bit D/A converter<span class="_ _1"></span>.</span></div><div class="t m1 xf hb y54 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls39 ws4a">Four general <span class="_ _3"></span>purpose T<span class="_ _a"></span>imers with two capture in<span class="_ _a"></span>puts each and up to four comp<span class="_ _3"></span>are </span></div><div class="t m1 x10 he y55 ff1 fs8 fc2 sc0 ls2a ws1c">output pins <span class="_ _6"></span>each. Each Timer block has<span class="_ _6"></span> an external <span class="_ _6"></span>count input.</div><div class="t m1 xf hb y56 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls38 ws2f">One PWM/T<span class="_ _a"></span>imer block with support for 3 <span class="_ _3"></span><span class="ls39 ws42">phase motor control.<span class="_ _3"></span><span class="ls48 ws2e"> The PWM has two </span></span></span></div><div class="t m1 x10 he y57 ff1 fs8 fc2 sc0 ls3e ws37">external count inp<span class="_ _3"></span>uts.</div><div class="t m1 xf hb y58 ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls17 ws1a">Real T<span class="_ _a"></span>ime <span class="_ _6"></span>Clock with separate power pin,<span class="ls35 ws4b"> clock source can be the R<span class="_ _a"></span>TC oscillator </span></span></div><div class="t m1 x10 he y59 ff1 fs8 fc2 sc0 ls35 ws4c">or the APB clock.</div><div class="t m1 xf hb y5a ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls2d ws1d">2<span class="_"> </span>kB S<span class="_ _a"></span>tatic RAM powered from the<span class="_ _a"></span> <span class="_ _6"></span>RTC power pin<span class="_ _3"></span>, allowing dat<span class="_ _3"></span>a to be stored </span></div><div class="t m1 x10 he y5b ff1 fs8 fc2 sc0 ls29 ws1b">when the rest of the chip is powered of<span class="_ _a"></span>f.</div><div class="t m1 xf hb y5c ff2 fs8 fc2 sc0 ls0 ws0">–<span class="_ _14"> </span><span class="ff1 ls28 ws19">W<span class="_ _a"></span>atchdog T<span class="_ _a"></span>imer<span class="_ _a"></span>. The watchdog timer can be clocked from the internal RC </span></div><div class="t m1 x10 he y5d ff1 fs8 fc2 sc0 ls30 ws4d">oscillator<span class="_ _a"></span>, the RTC osc<span class="ws4e">illator<span class="_ _1"></span>, or the APB clock.</span></div><div class="t m1 xe hc y5e ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls2d ws1d">S<span class="_ _a"></span>tandard ARM T<span class="_ _0"></span>est/Debug interface for comp<span class="_ _a"></span>atibility with existing tools.</span></div><div class="t m1 xe hc y5f ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls2d ws4f">Emulation T<span class="_ _a"></span>race Module </span></div><div class="t m1 xe hc y60 ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls49 ws50">supports real-time trac<span class="_ _6"></span>e.</span></div><div class="t m1 xf he y61 ff1 fs8 fc2 sc0 ls42 ws51">Single 3.3<span class="_"> </span>V power supply (3.0<span class="_"> </span>V to 3.6<span class="_"> </span>V).</div><div class="t m1 xf he y62 ff1 fs8 fc2 sc0 ls4a ws0">Four reduce<span class="_ _6"></span>d power mod<span class="_ _6"></span>es: Idle, Sleep,<span class="_ _6"></span> Power Down, <span class="_ _6"></span>and Deep Powe<span class="_ _6"></span>r down.</div><div class="t m1 xf he y63 ff1 fs8 fc2 sc0 ls3e ws52">Four external interr<span class="_ _3"></span>upt input<span class="_ _a"></span>s. In addition <span class="ls33 ws53">every PORT<span class="_ _a"></span>0/2 pin can be configured as an </span></div><div class="t m1 xf he y64 ff1 fs8 fc2 sc0 ls33 ws54">edge sensing inter<span class="_ _3"></span>rupt.</div><div class="t m1 xf he y65 ff1 fs8 fc2 sc0 ls28 ws19">Processor wakeup from Power Down mode vi<span class="_ _a"></span>a any interrupt able to operate during </div><div class="t m1 xf he y66 ff1 fs8 fc2 sc0 ls28 ws55">Power Down mode (include<span class="_ _3"></span>s external interrup<span class="_ _3"></span>ts, R<span class="_ _a"></span>TC interrupt, and Ethernet wakeup </div><div class="t m1 xf he y67 ff1 fs8 fc2 sc0 ls3e ws0">interrupt).</div><div class="t m1 xf he y68 ff1 fs8 fc2 sc0 ls3e ws37">T<span class="_ _1"></span>w<span class="_ _6"></span>o independent p<span class="_ _3"></span>ower domains allow fine tuning of power co<span class="_ _3"></span>nsumption based on </div><div class="t m1 xf he y69 ff1 fs8 fc2 sc0 ls4b ws56">needed fe<span class="_ _6"></span>atures.</div><div class="t m1 xf he y6a ff1 fs8 fc2 sc0 ls28 ws19">Brownout detect with sep<span class="_ _3"></span>arate thresholds for inter<span class="_ _3"></span>rupt and forced reset.</div><div class="t m1 xf he y6b ff1 fs8 fc2 sc0 ls30 ws4d">On-chip Power On Reset.</div><div class="t m1 xf he y6c ff1 fs8 fc2 sc0 ls35 ws4c">On-chip crystal oscillator with an op<span class="ls2e ws21">erating range of 1<span class="_"> </span>MHz to 24<span class="_"> </span>MHz.</span></div><div class="t m1 xf he y6d ff1 fs8 fc2 sc0 ls17 ws57">4<span class="_ _15"> </span>MHz internal RC oscillator that can optionally be used as<span class="ls41 ws58"> the system clock. For USB </span></div><div class="t m1 xf he y6e ff1 fs8 fc2 sc0 ls28 ws19">and CAN application, an external clo<span class="_ _a"></span>ck source is suggested to be used.</div><div class="t m1 xf he y6f ff1 fs8 fc2 sc0 ls2c ws59">On-chip PLL allows CPU opera<span class="ls3e ws52">tion up to<span class="_ _3"></span> the maximum CP<span class="ls3a ws5a">U rate without the <span class="_ _a"></span>need for </span></span></div><div class="t m1 xf he y70 ff1 fs8 fc2 sc0 ls4c ws5b">a high frequency crystal. May be run from<span class="ls41 ws5c"> the main oscillator<span class="_ _1"></span>, the internal R<span class="_ _6"></span>C </span></div><div class="t m1 xf he y71 ff1 fs8 fc2 sc0 ls4c ws5d">oscillator<span class="_ _a"></span>, or the RTC oscillator<span class="_ _1"></span>.</div><div class="t m1 xf he y72 ff1 fs8 fc2 sc0 ls4d ws5e">Boundary sc<span class="_ _6"></span>an for simplified b<span class="_ _6"></span>oard testing. (<span class="_ _6"></span>LPC2378 only)</div><div class="t m1 xf he y73 ff1 fs8 fc2 sc0 ls30 ws4d">V<span class="_ _a"></span>ersatile pin function selections allow mo<span class="ls2b ws5f">re possibilities for using on-chip peripheral </span></div><div class="t m1 xf he y74 ff1 fs8 fc2 sc0 ls4e ws0">functions.</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.610738,0.000000,0.000000,1.610738,-12.885906,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628329339b6e2b6d55d5bf9e/bg5.jpg"><div class="t m1 x5 h8 yb ff1 fs5 fc2 sc0 lsc ws0">UM1021<span class="_ _a"></span>1_<span class="_ _6"></span>1<span class="_ _8"> </span><span class="lsd ws7">© Koninklijke Ph<span class="_ _6"></span>ilips Electronics <span class="_ _6"></span>N.V<span class="_ _a"></span>. 2006. All ri<span class="_ _6"></span>ghts reserved.</span></div><div class="t m1 x5 h9 yc ff2 fs6 fc1 sc0 lse ws8">User manual <span class="_ _9"> </span>Rev<span class="_ _a"></span>. 01 — 6 October 2006 <span class="_ _b"> </span>5 of 612</div><div class="t m1 x5 hc y10 ff2 fs9 fc1 sc0 ls15 wsc">Philip<span class="_ _a"></span>s Semiconductors</div><div class="t m1 x6 hd y11 ff2 fsa fc1 sc0 ls16 ws0">UM1021<span class="_ _1"></span>1</div><div class="t m1 x11 hb y12 ff2 fs8 fc1 sc0 ls39 ws42">Chapter 1: LPC2300 Introduc<span class="_ _3"></span>tory information</div><div class="t m1 x5 ha y75 ff2 fs7 fc1 sc0 ls4f ws0">3.<span class="_ _13"> </span>Applications</div><div class="t m1 xe hc y4a ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls2e ws21">Industrial control</span></div><div class="t m1 xe hc y76 ff2 fs9 fc2 sc0 ls0 ws0">•<span class="_ _10"> </span><span class="ff1 fs8 ls40 ws3e">Medical systems</span></div><div class="t m1 x5 ha y77 ff2 fs7 fc1 sc0 ls27 ws60">4.<span class="_ _13"> </span>Ordering options</div><div class="t m1 x1 h2 y78 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m1 x1 h2 y79 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m1 x5 ha y7a ff2 fs7 fc1 sc0 lsf ws61">5.<span class="_ _13"> </span>Architectural overview</div><div class="t m1 x1 he y7b ff1 fs8 fc2 sc0 ls33 ws53">The LPC2300 consist<span class="_ _a"></span>s<span class="_ _6"></span> of an ARM7TDMI-S CP<span class="ls49 ws62">U with emulation supp<span class="_ _6"></span>ort, the ARM7 Local </span></div><div class="t m1 x1 he y7c ff1 fs8 fc2 sc0 ls29 ws1b">Bus for closely coupled, high speed access <span class="ls3e ws37">to th<span class="_ _a"></span>e majority <span class="_ _6"></span>of on-chip memo<span class="_ _3"></span>ry<span class="_ _1"></span>, the AMBA </span></div><div class="t m1 x1 he y7d ff1 fs8 fc2 sc0 ls28 ws63">Advanced High-performanc<span class="_ _3"></span>e Bus (AHB) interfacin<span class="ls13 ws64">g to high spe<span class="_ _3"></span>ed on-chip peri<span class="_ _3"></span>pherals and </span></div><div class="t m1 x1 he y7e ff1 fs8 fc2 sc0 ls33 ws2c">external memory<span class="_ _1"></span>, and the AMBA Advanced Periph<span class="_ _3"></span>eral Bus (APB) for connection to othe<span class="_ _a"></span>r </div><div class="t m1 x1 he y7f ff1 fs8 fc2 sc0 ls11 ws23">on-chip peripheral functions. The microcontr<span class="_ _3"></span>oller permanently configures the </div><div class="t m1 x1 he y80 ff1 fs8 fc2 sc0 ls2a ws1c">ARM7TDMI-S <span class="_ _6"></span>processor f<span class="_ _6"></span>or little-endia<span class="_ _6"></span>n byte order<span class="_ _3"></span>.</div><div class="t m1 x1 he y81 ff1 fs8 fc2 sc0 ls12 wsb">The microcontroller implement<span class="_ _a"></span>s two AHB buses in order to allow the Ethernet block to </div><div class="t m1 x1 he y82 ff1 fs8 fc2 sc0 ls14 ws3b">operate without interference cau<span class="_ _3"></span>sed by other system activity<span class="_ _1"></span>. The primary AHB, referred </div><div class="t m1 x1 he y83 ff1 fs8 fc2 sc0 ls14 ws3b">to as AHB1, includes the V<span class="_ _1"></span>ectored Interrupt Controller<span class="_ _a"></span>, General Purpose DMA Controller<span class="_ _1"></span>, </div><div class="t m1 x1 he y84 ff1 fs8 fc2 sc0 ls29 ws1b">External Memory Controller<span class="_ _1"></span>, USB interface, and a 8<span class="_"> </span>kB SRAM primarily intended for use </div><div class="t m1 x1 he y85 ff1 fs8 fc2 sc0 ls10 wsa">by the USB.</div><div class="t m1 x1 he y86 ff1 fs8 fc2 sc0 ls2c ws3a">The second AHB, referred to as AHB2, in<span class="ls11 ws23">cludes only the Ethernet block and an </span></div><div class="t m1 x1 he y87 ff1 fs8 fc2 sc0 ls10 ws3c">associated 16<span class="_"> </span>kB SRAM. In addition, a<span class="_ _3"></span> bus bridge is provided th<span class="_ _3"></span>at allows the secondary </div><div class="t m1 x1 he y88 ff1 fs8 fc2 sc0 ls11 ws23">AHB to be a bus master on AHB1, allowing expan<span class="_ _3"></span>sion of Ethernet buf<span class="_ _a"></span>fer <span class="_ _6"></span>space into </div><div class="t m1 x1 he y89 ff1 fs8 fc2 sc0 ls2d ws1d">off-chip memo<span class="_ _a"></span>ry or <span class="_ _6"></span>unused sp<span class="_ _a"></span>ace <span class="_ _6"></span>in memory residing on AHB1.</div><div class="t m1 x5 h6 y8a ff2 fs4 fc1 sc0 ls50 ws65">T<span class="_ _1"></span>able 1.<span class="_ _16"> </span>LPC2364/6/8/78 orderin<span class="_ _6"></span>g options</div><div class="t m1 x8 h6 y8b ff2 fs4 fc2 sc0 ls51 ws66">Ty<span class="_ _12"></span>p<span class="_ _6"></span>e<span class="_ _12"></span> n<span class="_ _12"></span>u<span class="_ _12"></span>m<span class="_ _6"></span>b<span class="_ _12"></span>e<span class="_ _12"></span>r<span class="_ _17"> </span><span class="ls52 ws0">Flash</span></div><div class="t m1 x1d h6 y8c ff2 fs4 fc2 sc0 ls9 ws0">(kB)</div><div class="t m1 x1e h6 y8b ff2 fs4 fc2 sc0 ls53 ws0">SRAM(kB)<span class="_ _5"> </span><span class="ls54">Ethernet<span class="_ _18"> </span><span class="ls9">USB </span></span></div><div class="t m1 x1f h6 y8c ff2 fs4 fc2 sc0 ls55 ws67">dev + </div><div class="t m1 x1f h6 y8d ff2 fs4 fc2 sc0 ls21 ws0">4kB </div><div class="t m1 x1f h6 y8e ff2 fs4 fc2 sc0 ls56 ws0">FIFO</div><div class="t m1 x20 h6 y8b ff2 fs4 fc2 sc0 lsa ws0">CAN<span class="_ _19"> </span><span class="ls57">SD/</span></div><div class="t m1 x21 h6 y8c ff2 fs4 fc2 sc0 ls58 ws0">MMC</div><div class="t m1 x22 h6 y8b ff2 fs4 fc2 sc0 ls18 ws0">GP </div><div class="t m1 x22 h6 y8c ff2 fs4 fc2 sc0 ls59 ws0">DMA</div><div class="t m1 x23 h6 y8b ff2 fs4 fc2 sc0 lsa ws0">ADC<span class="_ _19"> </span>DAC<span class="_ _19"> </span><span class="ls5a">Te<span class="_ _12"></span>m<span class="_ _12"></span>p<span class="_ _12"></span> </span></div><div class="t m1 x24 h6 y8c ff2 fs4 fc2 sc0 ls5b ws0">range</div><div class="t m1 x25 h6 y8f ff2 fs4 fc2 sc0 ls1c ws0">Local </div><div class="t m1 x25 h6 y90 ff2 fs4 fc2 sc0 ls56 ws0">bus</div><div class="t m1 x26 h6 y8f ff2 fs4 fc2 sc0 ls5c ws0">Ether<span class="_ _a"></span>. </div><div class="t m1 x26 h6 y90 ff2 fs4 fc2 sc0 ls5d ws0">buff</div><div class="t m1 x27 h6 y8f ff2 fs4 fc2 sc0 ls1c ws0">GP/</div><div class="t m1 x27 h6 y90 ff2 fs4 fc2 sc0 ls57 ws0">USB</div><div class="t m1 x28 h6 y8f ff2 fs4 fc2 sc0 ls5e ws0">RTC<span class="_ _1a"> </span><span class="ls51">To<span class="_ _12"></span>t<span class="_ _6"></span>a<span class="_ _12"></span>l</span></div><div class="t m1 x8 h10 y91 ff1 fs4 fc2 sc0 ls22 ws68">LPC2364FB100<span class="_ _19"> </span>128<span class="_ _1b"> </span>8<span class="_ _1c"> </span>16<span class="_ _1d"> </span>8<span class="_ _1d"> </span>2<span class="_ _1e"> </span>34<span class="_ _1f"> </span>RMII<span class="_ _20"> </span>yes<span class="_ _1b"> </span>2 ch<span class="_ _21"> </span>no<span class="_ _22"> </span>yes<span class="_ _13"> </span>6 ch<span class="_ _21"> </span>1 ch<span class="_ _21"> </span><span class="ff5 ls0 ws0">−<span class="ff1 ls1d">40<span class="_"> </span></span>°</span><span class="ls57 ws69">C to </span></div><div class="t m1 x24 h10 y92 ff1 fs4 fc2 sc0 ls5f ws0">+85<span class="_"> </span><span class="ff5 ls0">°<span class="ff1">C</span></span></div><div class="t m1 x8 h10 y93 ff1 fs4 fc2 sc0 ls1c wse">LPC2366FB100<span class="_ _19"> </span>256<span class="_ _1b"> </span>32<span class="_ _23"> </span>16<span class="_ _1d"> </span>8<span class="_ _1d"> </span>2<span class="_ _1e"> </span>58<span class="_ _1f"> </span>RMII<span class="_ _20"> </span>yes<span class="_ _1b"> </span>2 ch<span class="_ _21"> </span>no<span class="_ _22"> </span>yes<span class="_ _13"> </span>6 ch<span class="_ _21"> </span>1 ch<span class="_ _21"> </span><span class="ff5 ls0 ws0">−<span class="ff1 ls1d">40<span class="_"> </span></span>°</span><span class="ls57 ws69">C to </span></div><div class="t m1 x24 h10 y94 ff1 fs4 fc2 sc0 ls5f ws0">+85<span class="_"> </span><span class="ff5 ls0">°<span class="ff1">C</span></span></div><div class="t m1 x8 h10 y95 ff1 fs4 fc2 sc0 ls1c wse">LPC2368FB100<span class="_ _19"> </span>512<span class="_ _1b"> </span>32<span class="_ _23"> </span>16<span class="_ _1d"> </span>8<span class="_ _1d"> </span>2<span class="_ _1e"> </span>58<span class="_ _1f"> </span>RMII<span class="_ _20"> </span>yes<span class="_ _1b"> </span>2 ch<span class="_ _21"> </span>yes<span class="_ _24"> </span>yes<span class="_ _13"> </span>6 ch<span class="_ _21"> </span>1 ch<span class="_ _21"> </span><span class="ff5 lsa ws0">−4<span class="ff1 ls0">0<span class="_"> </span><span class="ff5">°</span><span class="ls60 ws6a">C to </span></span></span></div><div class="t m1 x24 h10 y96 ff1 fs4 fc2 sc0 ls5f ws0">+85<span class="_"> </span><span class="ff5 ls0">°<span class="ff1">C</span></span></div><div class="t m1 x5 h6 y97 ff2 fs4 fc1 sc0 lsa wsf">T<span class="_ _1"></span>able 2.<span class="_ _16"> </span>LPC2378 ordering optio<span class="_ _6"></span>ns</div><div class="t m1 x8 h6 y98 ff2 fs4 fc2 sc0 ls51 ws66">Ty<span class="_ _12"></span>p<span class="_ _6"></span>e<span class="_ _12"></span> n<span class="_ _12"></span>u<span class="_ _12"></span>m<span class="_ _6"></span>b<span class="_ _12"></span>e<span class="_ _12"></span>r<span class="_ _25"> </span><span class="ls61 ws0">Flash</span></div><div class="t m1 x29 h6 y99 ff2 fs4 fc2 sc0 ls62 ws0">(kB)</div><div class="t m1 x2a h6 y98 ff2 fs4 fc2 sc0 ls1f ws0">SRAM(kB)<span class="_ _26"> </span><span class="ls63 ws6b">Ext Bus<span class="_ _27"> </span></span><span class="ls5c">Ether</span></div><div class="t m1 x2b h6 y99 ff2 fs4 fc2 sc0 ls52 ws0">net</div><div class="t m1 x2c h6 y98 ff2 fs4 fc2 sc0 ls9 ws0">USB </div><div class="t m1 x2c h6 y99 ff2 fs4 fc2 sc0 lsb ws6c">dev + </div><div class="t m1 x2c h6 y9a ff2 fs4 fc2 sc0 ls21 ws0">4kB </div><div class="t m1 x2c h6 y9b ff2 fs4 fc2 sc0 ls52 ws0">FIFO</div><div class="t m1 x2d h6 y98 ff2 fs4 fc2 sc0 lsa ws0">CAN<span class="_ _19"> </span><span class="ls57">SD/</span></div><div class="t m1 x21 h6 y99 ff2 fs4 fc2 sc0 ls58 ws0">MMC</div><div class="t m1 x22 h6 y98 ff2 fs4 fc2 sc0 ls64 ws0">GP </div><div class="t m1 x22 h6 y99 ff2 fs4 fc2 sc0 ls59 ws0">DMA</div><div class="t m1 x2e h6 y98 ff2 fs4 fc2 sc0 lsa ws0">ADC<span class="_ _18"> </span>DAC<span class="_ _19"> </span><span class="ls51">Te<span class="_ _12"></span>m<span class="_ _12"></span>p<span class="_ _12"></span> </span></div><div class="t m1 x24 h6 y99 ff2 fs4 fc2 sc0 ls9 ws0">range</div><div class="t m3 xf h6 y9c ff2 fs4 fc2 sc0 ls65 ws6d">Local bus</div><div class="t m3 x2f h6 y9c ff2 fs4 fc2 sc0 ls0 ws6e">Ether<span class="_ _a"></span>. buff</div><div class="t m3 x30 h6 y9c ff2 fs4 fc2 sc0 ls1b ws0">GP/USB</div><div class="t m3 x31 h6 y9c ff2 fs4 fc2 sc0 ls66 ws0">RTC</div><div class="t m3 x32 h6 y9c ff2 fs4 fc2 sc0 ls5a ws0">To<span class="_ _12"></span>t<span class="_ _6"></span>a<span class="_ _12"></span>l</div><div class="t m0 x8 h7 y9d ff1 fs4 fc2 sc0 ls1e ws0">LPC2378FBD144<span class="_ _18"> </span>512<span class="_ _1b"> </span>32<span class="_ _28"> </span>16<span class="_ _28"> </span>8<span class="_ _16"> </span>2<span class="_ _1b"> </span>58<span class="_ _28"> </span>MiniBus:</div><div class="t m0 x33 h7 y9e ff1 fs4 fc2 sc0 ls1a ws6f">8 data, </div><div class="t m0 x33 h7 y9f ff1 fs4 fc2 sc0 ls67 ws70">16 addr </div><div class="t m0 x33 h7 ya0 ff1 fs4 fc2 sc0 ls59 ws71">& 2 cs</div><div class="t m0 x2b h10 y9d ff1 fs4 fc2 sc0 ls68 ws72">RMII<span class="_ _29"> </span>yes<span class="_ _1b"> </span>2 ch<span class="_ _21"> </span>yes<span class="_ _24"> </span>yes<span class="_ _29"> </span>8 ch<span class="_ _2a"> </span>1 ch<span class="_ _21"> </span><span class="ff5 ls0 ws0">−<span class="ff1 ls69">40<span class="_"> </span></span>°</span><span class="ls6a ws73">C to </span></div><div class="t m0 x24 h10 y9e ff1 fs4 fc2 sc0 ls4 ws0">+85<span class="_"> </span><span class="ff5 ls0">°<span class="ff1">C</span></span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.610738,0.000000,0.000000,1.610738,-12.885906,0.000000]}'></div></div>
