xilinx dft ip手册_手册资料_源码/资料下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/628c906ebc2d3963da84ceaa/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c906ebc2d3963da84ceaa/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Discrete Fourier </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">T<span class="_ _0"></span>ransform v4.2</div><div class="t m0 x1 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">LogiCORE IP Product Guide</div><div class="t m0 x1 h4 y4 ff1 fs2 fc0 sc0 ls3 ws3">Viv<span class="_ _1"></span>ado Design Suite</div><div class="t m0 x1 h5 y5 ff1 fs3 fc0 sc0 ls4 ws4">PG106 December 10, 2020</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c906ebc2d3963da84ceaa/bg2.jpg"><div class="t m0 x2 h6 y6 ff3 fs4 fc0 sc0 ls5 ws5">Discret<span class="_ _1"></span>e Fourier T<span class="_ _2"></span>rans<span class="_ _1"></span>form v4.2<span class="_ _3"> </span>2</div><div class="t m0 x2 h7 y7 ff4 fs4 fc0 sc0 ls6 ws6">PG106 December 10, 2020<span class="_ _4"> </span><span class="fc1 ls7 ws7">www<span class="_ _2"></span>.xil<span class="_ _5"></span>inx.com</span></div><div class="t m0 x2 h8 y8 ff4 fs1 fc0 sc0 ls8 ws8">T<span class="_ _6"></span>able of Con<span class="_ _1"></span>t<span class="_ _1"></span>en<span class="_ _1"></span>ts</div><div class="t m0 x3 h9 y9 ff3 fs2 fc0 sc0 ls9 ws9">IP Facts</div><div class="t m0 x3 h9 ya ff3 fs2 fc0 sc0 ls1 ws7">Chapter<span class="_"> </span>1:<span class="_ _7"> </span>Overview</div><div class="t m0 x4 h6 yb ff3 fs4 fc0 sc0 lsa wsa">Navigating Con<span class="_ _5"></span>tent by Design P<span class="_ _5"></span>rocess<span class="_ _8"> </span>. . <span class="lsb wsb">. . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . <span class="_ _9"> </span> 5</span></div><div class="t m0 x4 h6 yc ff3 fs4 fc0 sc0 lsb wsb">Feature Summary<span class="_ _5"></span>. . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span><span class="wsc">. . . . . . . . . . <span class="_ _9"> </span> 5</span></div><div class="t m0 x4 h6 yd ff3 fs4 fc0 sc0 lsb wsc">Applications<span class="_ _a"></span> . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . . . <span class="_ _9"> </span> 6</div><div class="t m0 x4 h6 ye ff3 fs4 fc0 sc0 lsb wsc">Licensing and Ordering Information<span class="_ _b"> </span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . .<span class="lsc wsd"> . . . . <span class="_ _9"> </span> 6</span></div><div class="t m0 x3 h9 yf ff3 fs2 fc0 sc0 lsd wse">Chapter<span class="_"> </span>2:<span class="_ _7"> </span>Product Specification</div><div class="t m0 x4 h6 y10 ff3 fs4 fc0 sc0 lsb wsb">Performance<span class="_ _a"></span>. . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . <span class="_ _5"></span><span class="wsc">. . . . . . . . . . . . <span class="_ _9"> </span> 8</span></div><div class="t m0 x4 h6 y11 ff3 fs4 fc0 sc0 lsb wsc">Resource Utilization<span class="_ _a"></span>. . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . .<span class="wsb"> . . . . . . . . . . <span class="_ _9"> </span> 9</span></div><div class="t m0 x4 h6 y12 ff3 fs4 fc0 sc0 lsb wsb">Port Descriptions<span class="_ _c"></span> . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . .<span class="lse wsf"> . . . . . . . . . . . <span class="_ _9"> </span> 9</span></div><div class="t m0 x3 h9 y13 ff3 fs2 fc0 sc0 lsf ws7">Chapter<span class="_"> </span>3:<span class="_ _7"> </span>Designin<span class="ls9 ws10">g with the Core</span></div><div class="t m0 x4 h6 y14 ff3 fs4 fc0 sc0 ls10 wsb">Clocking. . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . .<span class="ls11"> . . . . <span class="_ _5"></span>. . . . . . . . . <span class="_ _9"> </span> 10</span></div><div class="t m0 x4 h6 y15 ff3 fs4 fc0 sc0 lsb wsb">Resets<span class="_ _c"></span> . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . <span class="_ _9"> </span> 10</div><div class="t m0 x4 h6 y16 ff3 fs4 fc0 sc0 lsb wsc">Protocol Description<span class="_ _8"> </span> . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . . <span class="_ _9"> </span> 10</div><div class="t m0 x4 h6 y17 ff3 fs4 fc0 sc0 lsb wsc">Encoding of Size Parameter<span class="_ _c"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . .<span class="ls11 ws11"> <span class="_ _5"></span>. . . . . . <span class="_ _9"> </span> 12</span></div><div class="t m0 x3 h9 y18 ff3 fs2 fc0 sc0 lsd ws12">Chapter<span class="_"> </span>4:<span class="_ _7"> </span>Design Flow Steps</div><div class="t m0 x4 h6 y19 ff3 fs4 fc0 sc0 ls10 wsc">Customizing and Generating the Core<span class="_ _b"> </span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . .<span class="ls12 ws13"> . . <span class="_ _9"> </span> 19</span></div><div class="t m0 x4 h6 y1a ff3 fs4 fc0 sc0 ls10 wsc">Constraining the Core<span class="_ _8"> </span> . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . .<span class="lse wsf"> . . . . . . . . <span class="_ _9"> </span> 21</span></div><div class="t m0 x4 h6 y1b ff3 fs4 fc0 sc0 ls10 wsc">Simulation<span class="_ _9"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . <span class="_ _9"> </span> 21</div><div class="t m0 x4 h6 y1c ff3 fs4 fc0 sc0 ls10 wsc">Synthesis and Implementation<span class="_ _8"> </span>. . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . .<span class="ls13 ws14"> . . . . <span class="_ _9"> </span> 22</span></div><div class="t m0 x3 h9 y1d ff3 fs2 fc0 sc0 ls9 ws15">Chapter<span class="_"> </span>5:<span class="_ _7"> </span>C Model</div><div class="t m0 x4 h6 y1e ff3 fs4 fc0 sc0 ls10 wsc">Features<span class="_ _d"> </span> . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . <span class="_ _5"></span><span class="wsb">. . . . . . . . . . . . . <span class="_ _9"> </span> 23</span></div><div class="t m0 x4 h6 y1f ff3 fs4 fc0 sc0 ls10 wsb">Overview<span class="_ _9"> </span> . . . . . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . <span class="wsc">. . . <span class="_ _5"></span>. . . . . . . . . <span class="_ _9"> </span> 23</span></div><div class="t m0 x4 h6 y20 ff3 fs4 fc0 sc0 ls10 wsb">Unpacking and Model Contents<span class="_ _c"></span> . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . <span class="_ _5"></span><span class="wsc">. . . . <span class="_ _9"> </span> 23</span></div><div class="t m0 x4 h6 y21 ff3 fs4 fc0 sc0 ls10 wsb">Installation<span class="_ _5"></span> . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . <span class="_ _5"></span>. . . . . . <span class="_ _9"> </span> 24</div><div class="t m0 x4 h6 y22 ff3 fs4 fc0 sc0 ls10 wsb">DFT C Model Interface<span class="_ _d"> </span>. <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. <span class="wsc">. . <span class="_ _5"></span>. . . . . . <span class="_ _e"> </span> 24</span></div><div class="t m0 x4 h6 y23 ff3 fs4 fc0 sc0 lse wsf">Compiling with the DFT C Model<span class="_ _e"> </span> . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . <span class="ls10 wsc">. . . . <span class="_ _e"> </span> 27</span></div><div class="t m0 x4 h6 y24 ff3 fs4 fc0 sc0 ls10 wsc">DFT MATLAB MEX Function. . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . <span class="_ _5"></span>. . . . . <span class="_ _e"> </span> 28</div><div class="c x5 y25 w2 ha"><div class="t m1 x6 hb y26 ff5 fs5 fc2 sc0 ls1 ws7"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" 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<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c906ebc2d3963da84ceaa/bg3.jpg"><div class="t m0 x2 h6 y6 ff3 fs4 fc0 sc0 ls5 ws5">Discret<span class="_ _1"></span>e Fourier T<span class="_ _2"></span>rans<span class="_ _1"></span>form v4.2<span class="_ _3"> </span>3</div><div class="t m0 x2 h7 y7 ff4 fs4 fc0 sc0 ls6 ws6">PG106 December 10, 2020<span class="_ _4"> </span><span class="fc1 ls7 ws7">www<span class="_ _2"></span>.xil<span class="_ _5"></span>inx.com</span></div><div class="t m0 x3 h9 y27 ff3 fs2 fc0 sc0 ls14 ws16">Appendix<span class="_"> </span>A:<span class="_ _7"> </span>Migrating and Upgrading</div><div class="t m0 x4 h6 y28 ff3 fs4 fc0 sc0 lse wsf">Upgrading in the Vivado Design Suite<span class="_"> </span> . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="ls10 wsc">. . . <span class="_ _e"> </span> 29</span></div><div class="t m0 x3 h9 y29 ff3 fs2 fc0 sc0 ls14 ws7">Appendix<span class="_"> </span>B:<span class="_ _7"> </span>Debugging</div><div class="t m0 x4 h6 y2a ff3 fs4 fc0 sc0 ls10 wsc">Finding Help on Xilinx.com<span class="_ _b"> </span> . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . <span class="_ _e"> </span> 30</div><div class="t m0 x4 h6 y2b ff3 fs4 fc0 sc0 ls10 wsb">Debug Tools<span class="_ _b"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . .<span class="_ _5"></span><span class="lse wsf"> . . . . . . . . . <span class="_ _5"></span>. . <span class="_ _e"> </span> 31</span></div><div class="t m0 x4 h6 y2c ff3 fs4 fc0 sc0 lsb wsb">Simulation Debug<span class="_ _5"></span>. . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . .<span class="ls11"> <span class="_ _5"></span>. . . . . . . . . <span class="_ _e"> </span> 32</span></div><div class="t m0 x3 h9 y2d ff3 fs2 fc0 sc0 ls15 ws17">Appendix<span class="_"> </span>C:<span class="_ _7"> </span>Additional Reso<span class="ls9 ws18">urces and Legal Notices</span></div><div class="t m0 x4 h6 y2e ff3 fs4 fc0 sc0 ls10 wsc">Xilinx Resources<span class="_"> </span>. . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . .<span class="lse wsf"> . <span class="_ _5"></span>. . . . . . . . . <span class="_ _e"> </span> 33</span></div><div class="t m0 x4 h6 y2f ff3 fs4 fc0 sc0 ls10 wsc">References<span class="_ _b"> </span> . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . <span class="_ _5"></span>. . <span class="_ _e"> </span> 33</div><div class="t m0 x4 h6 y30 ff3 fs4 fc0 sc0 ls10 wsc">Revision History<span class="_"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . .<span class="_ _5"></span><span class="lse wsf"> . . . . . . . . . . <span class="_ _e"> </span> 34</span></div><div class="t m0 x4 h6 y31 ff3 fs4 fc0 sc0 lsb wsb">Please Read: Important Legal Notices<span class="_ _b"> </span> . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _5"></span>. . . . . . <span class="wsc">. . . <span class="_ _e"> </span> 34</span></div><div class="c x5 y25 w2 ha"><div class="t m1 x6 hb y26 ff5 fs5 fc2 sc0 ls1 ws7"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c906ebc2d3963da84ceaa/bg4.jpg"><div class="t m0 x2 h6 y6 ff3 fs4 fc0 sc0 ls5 ws5">Discret<span class="_ _1"></span>e Fourier T<span class="_ _2"></span>rans<span class="_ _1"></span>form v4.2<span class="_ _3"> </span>4</div><div class="t m0 x2 h7 y7 ff4 fs4 fc0 sc0 ls6 ws6">PG106 December 10, 2020<span class="_ _4"> </span><span class="fc1 ls7 ws7">www<span class="_ _2"></span>.xil<span class="_ _5"></span>inx.com<span class="_ _f"> </span><span class="fc0 ls16 ws19">Product Specification</span></span></div><div class="t m0 x2 hc y32 ff3 fs6 fc0 sc0 ls17 ws7">Intr<span class="_ _1"></span>oduction</div><div class="t m0 x2 hd y33 ff6 fs4 fc0 sc0 ls18 ws1a">The Xilinx® LogiC<span class="_ _1"></span>ORE<span class="_ _a"></span>™ IP Discrete Fourier </div><div class="t m0 x2 hd y34 ff6 fs4 fc0 sc0 ls19 ws1b">T<span class="_ _2"></span>ransform (DFT) core meets the requirements </div><div class="t m0 x2 he y35 ff6 fs4 fc0 sc0 ls1a ws19">for 3GPP Long T<span class="_ _2"></span>erm Evolution (L<span class="_ _2"></span>TE)<span class="ff1 fc4 ls1 ws7"> <span class="ff6 fc1 ls1b">[Ref<span class="_"> </span>1]<span class="fc0 ws1c"> and </span></span></span></div><div class="t m0 x2 hd y36 ff6 fs4 fc0 sc0 ls1b ws1b">3GPP 5G-New Radio (5G-NR) <span class="fc1 ws7">[R<span class="_ _1"></span>ef<span class="_"> </span>2]<span class="fc0 ls1c ws1d"> systems.</span></span></div><div class="t m0 x2 hd y37 ff6 fs4 fc0 sc0 ls1d ws1e">The point size of the t<span class="_ _1"></span>ransform (N) can be </div><div class="t m0 x2 hd y38 ff6 fs4 fc0 sc0 ls18 ws1a">specified on a frame-by-frame basis and can </div><div class="t m0 x2 hd y39 ff6 fs4 fc0 sc0 ls1e ws1f">take the values N=2</div><div class="t m0 x7 hf y3a ff6 fs7 fc0 sc0 ls1 ws7">M</div><div class="t m0 x8 hd y3b ff6 fs4 fc0 sc0 ls1d ws7">*3</div><div class="t m0 x9 hf y3a ff6 fs7 fc0 sc0 ls1 ws7">P</div><div class="t m0 xa hd y3b ff6 fs4 fc0 sc0 ls1f ws7">*5</div><div class="t m0 xb hf y3a ff6 fs7 fc0 sc0 ls1 ws7">Q</div><div class="t m0 xc hd y3b ff6 fs4 fc0 sc0 ls20 ws20">, where M, P, and Q </div><div class="t m0 x2 hd y3c ff6 fs4 fc0 sc0 ls21 ws21">can be set to a range of values (as in <span class="fc1 ls22 ws7">Ta<span class="_ _b"></span>b<span class="_ _a"></span>l<span class="_ _b"> </span>e<span class="_ _10"> </span>3<span class="_ _b"></span>-<span class="_ _a"></span>1<span class="_ _b"> </span><span class="fc0 ls23">) </span></span></div><div class="t m0 x2 hd y3d ff6 fs4 fc0 sc0 ls24 ws22">that meet the L<span class="_ _2"></span>TE and 5G-NR system </div><div class="t m0 x2 hd y3e ff6 fs4 fc0 sc0 ls1e ws7">requirements.</div><div class="t m0 x2 hc y3f ff3 fs6 fc0 sc0 ls25 ws7">Fe<span class="_ _5"></span>at<span class="_ _5"></span>u<span class="_ _5"></span>r<span class="_ _5"></span>e<span class="_ _5"></span>s</div><div class="t m0 x2 hd y40 ff6 fs4 fc0 sc0 ls1e ws23">•<span class="_ _11"> </span>Support for wide range of transform sizes, </div><div class="t m0 xd hd y41 ff6 fs4 fc0 sc0 ls19 ws1b">including 1296 and 1536 up to 3240</div><div class="t m0 x2 hd y42 ff6 fs4 fc0 sc0 ls26 ws24">•<span class="_ _11"> </span>Less than 26 <span class="ff7 ls1 ws7">μ<span class="_ _5"></span></span><span class="ls27 ws25">s total latency when </span></div><div class="t m0 xd hd y43 ff6 fs4 fc0 sc0 ls26 ws26">transforming 1200 <span class="_ _5"></span>points at 245.76 MHz </div><div class="t m0 xd hd y44 ff6 fs4 fc0 sc0 ls1e ws23">(using any combination of sizes)</div><div class="t m0 x2 hd y45 ff6 fs4 fc0 sc0 ls1b ws27">•<span class="_ _11"> </span>Size can be changed for each transform</div><div class="t m0 x2 hd y46 ff6 fs4 fc0 sc0 ls28 ws28">•<span class="_ _11"> </span>Up to 18-bit twos co<span class="_ _1"></span>mplement input data </div><div class="t m0 xd hd y47 ff6 fs4 fc0 sc0 ls26 ws7">width</div><div class="t m0 x2 hd y48 ff6 fs4 fc0 sc0 ls29 ws29">•<span class="_ _11"> </span>Up to 18-bit twos complement output dat<span class="_ _1"></span>a </div><div class="t m0 xd hd y49 ff6 fs4 fc0 sc0 ls2a ws2a">width with 4-bit block exponent</div><div class="t m0 x2 hd y4a ff6 fs4 fc0 sc0 ls26 ws26">•<span class="_ _11"> </span>Direct and inverse DFT <span class="_ _5"></span>supported on </div><div class="t m0 xd hd y4b ff6 fs4 fc0 sc0 ls2b ws2b">frame-by-frame basis</div><div class="t m0 xe h10 y4c ff3 fs8 fc0 sc0 ls2c ws2c">IP F<span class="_ _2"></span>acts</div><div class="t m0 xf h6 y4d ff3 fs4 fc0 sc0 ls2d ws2d">LogiCORE IP F<span class="_ _1"></span>acts T<span class="_ _2"></span>able</div><div class="t m0 x10 h6 y4e ff3 fs4 fc0 sc0 ls2e ws2e">Core Specifics</div><div class="t m0 x11 h11 y4f ff6 fs9 fc0 sc0 ls2f ws7">Supported </div><div class="t m0 x11 h11 y50 ff6 fs9 fc0 sc0 ls30 ws2f">Device F<span class="_ _1"></span>ami<span class="_ _1"></span>ly</div><div class="t m0 x12 h12 y51 ff6 fsa fc1 sc0 ls31 ws7">(1)</div><div class="t m0 x13 h11 y52 ff6 fs9 fc0 sc0 ls32 ws7">UltraScale+™</div><div class="t m0 x14 h11 y53 ff6 fs9 fc0 sc0 ls33 ws7">UltraScale™</div><div class="t m0 x15 h11 y54 ff6 fs9 fc0 sc0 ls34 ws30">Ve<span class="_ _c"></span>r<span class="_ _5"></span>s<span class="_ _a"></span>a<span class="_ _5"></span>l<span class="_ _c"></span>™<span class="_ _c"></span> A<span class="_ _c"></span>C<span class="_ _5"></span>A<span class="_ _c"></span>P</div><div class="t m0 x16 h11 y55 ff6 fs9 fc0 sc0 ls35 ws31">Zynq®<span class="_ _1"></span>-7000 SoC</div><div class="t m0 x17 h11 y56 ff6 fs9 fc0 sc0 ls36 ws32">7 Series</div><div class="t m0 x11 h11 y57 ff6 fs9 fc0 sc0 ls2f ws33">Supported User </div><div class="t m0 x11 h11 y58 ff6 fs9 fc0 sc0 ls37 ws7">Interfaces</div><div class="t m0 x18 h11 y59 ff6 fs9 fc0 sc0 ls38 ws7">N/A</div><div class="t m0 x11 h11 y5a ff6 fs9 fc0 sc0 ls39 ws7">Res<span class="_ _5"></span>o<span class="_ _5"></span>u<span class="_ _5"></span>r<span class="_ _5"></span>ce<span class="_ _5"></span>s</div><div class="t m3 x19 h11 y5b ff6 fs9 fc1 sc0 ls3a ws34">P<span class="_ _1"></span>erformance <span class="_ _1"></span>and R<span class="_ _1"></span>esource<span class="_ _1"></span> Utilization web<span class="_ _1"></span> page</div><div class="t m0 x1a h6 y5c ff3 fs4 fc0 sc0 ls3b wsa">Provided with Cor<span class="_ _1"></span>e</div><div class="t m0 x11 h11 y5d ff6 fs9 fc0 sc0 ls3c ws35">Design Files<span class="_ _12"> </span> E<span class="_ _1"></span>n<span class="_ _1"></span>c<span class="_ _1"></span>r<span class="_ _1"></span>y<span class="_ _1"></span>p<span class="_ _1"></span>t<span class="_ _1"></span>ed<span class="_ _1"></span> <span class="_ _1"></span>R<span class="_ _2"></span>TL</div><div class="t m0 x11 h11 y5e ff6 fs9 fc0 sc0 ls3d ws36">Example <span class="_ _5"></span>Des<span class="_ _5"></span>ign<span class="_ _13"> </span> No<span class="_ _1"></span>t<span class="_ _1"></span> P<span class="_ _1"></span>r<span class="_ _1"></span>o<span class="_ _1"></span>vi<span class="_ _1"></span>d<span class="_ _1"></span>e<span class="_ _1"></span>d</div><div class="t m0 x11 h11 y5f ff6 fs9 fc0 sc0 ls3e ws37">T<span class="_ _2"></span>est Bench<span class="_ _14"> </span> N<span class="_ _1"></span>o<span class="_ _1"></span>t<span class="_ _1"></span> P<span class="_ _1"></span>r<span class="_ _1"></span>o<span class="_ _1"></span>v<span class="_ _1"></span>i<span class="_ _1"></span>d<span class="_ _1"></span>e<span class="_ _1"></span>d</div><div class="t m0 x11 h11 y60 ff6 fs9 fc0 sc0 ls3f ws38">Constraints <span class="_ _5"></span>File<span class="_ _15"> </span> N<span class="_ _1"></span>ot<span class="_ _1"></span> P<span class="_ _1"></span>r<span class="_ _1"></span>o<span class="_ _1"></span>v<span class="_ _1"></span>i<span class="_ _1"></span>de<span class="_ _2"></span>d</div><div class="t m0 x11 h11 y61 ff6 fs9 fc0 sc0 ls40 ws7">Simulation </div><div class="t m0 x11 h11 y62 ff6 fs9 fc0 sc0 ls41 ws7">Model</div><div class="t m0 x1b h11 y63 ff6 fs9 fc0 sc0 ls42 ws39">VHDL Behavioral</div><div class="t m0 x1c h11 y64 ff6 fs9 fc0 sc0 ls43 ws3a">VHDL or V<span class="_ _2"></span>erilog S<span class="_ _1"></span>tructural</div><div class="t m0 x1d h11 y65 ff6 fs9 fc0 sc0 ls44 ws3b">C Model</div><div class="t m0 x11 h11 y66 ff6 fs9 fc0 sc0 ls2f ws7">Supported </div><div class="t m0 x11 h11 y67 ff6 fs9 fc0 sc0 ls45 ws3c">S/W Driver</div><div class="t m0 x18 h11 y68 ff6 fs9 fc0 sc0 ls38 ws7">N/A</div><div class="t m0 x1e h6 y69 ff3 fs4 fc0 sc0 ls46 ws3d">T<span class="_ _2"></span>es<span class="_ _1"></span>ted Design Flows</div><div class="t m0 x1f h13 y6a ff3 fs7 fc1 sc0 ls47 ws7">(2)</div><div class="t m0 x11 h11 y6b ff6 fs9 fc0 sc0 ls48 ws3e">De<span class="_ _5"></span>s<span class="_ _c"></span>ig<span class="_ _5"></span>n<span class="_ _5"></span> E<span class="_ _5"></span>n<span class="_ _5"></span>t<span class="_ _5"></span>r<span class="_ _5"></span>y<span class="_ _16"> </span>Vivado® Design Suite</div><div class="t m0 x11 h11 y6c ff6 fs9 fc0 sc0 ls49 ws7">Simulation</div><div class="t m0 x20 h11 y6d ff6 fs9 fc0 sc0 ls4a ws3f">For supported simulators<span class="_ _5"></span>, see th<span class="_ _5"></span>e</div><div class="t m0 x21 h11 y6e ff6 fs9 fc1 sc0 ls4a ws3f">Xilinx Design T<span class="_ _2"></span>ools: Release Notes Guide.</div><div class="t m0 x11 h11 y6f ff6 fs9 fc0 sc0 ls35 ws40">Syn<span class="_ _5"></span>t<span class="_ _5"></span>h<span class="_ _5"></span>e<span class="_ _5"></span>s<span class="_ _5"></span>i<span class="_ _5"></span>s<span class="_ _17"> </span>Vivado S<span class="_ _1"></span>ynthesis</div><div class="t m0 x22 h6 y70 ff3 fs4 fc0 sc0 ls4b ws7">Support</div><div class="t m0 x11 h11 y71 ff6 fs9 fc0 sc0 ls39 ws41">Rel<span class="_ _5"></span>e<span class="_ _5"></span>a<span class="_ _5"></span>s<span class="_ _5"></span>e N<span class="_ _5"></span>o<span class="_ _5"></span>t<span class="_ _5"></span>e<span class="_ _5"></span>s </div><div class="t m0 x11 h11 y72 ff6 fs9 fc0 sc0 ls3e ws42">and Known </div><div class="t m0 x11 h11 y73 ff6 fs9 fc0 sc0 ls3d ws7">Issues</div><div class="t m0 x23 h11 y72 ff6 fs9 fc0 sc0 ls4c ws43">Master Answ<span class="_ _5"></span>er Record:<span class="fc1 ls38 ws44"> 54475</span></div><div class="t m0 x11 h11 y74 ff6 fs9 fc0 sc0 ls4d ws45">All Vivado IP </div><div class="t m0 x11 h11 y75 ff6 fs9 fc0 sc0 ls4e ws46">Change Logs</div><div class="t m0 x24 h11 y76 ff6 fs9 fc0 sc0 ls4f ws47">Master Vivado I<span class="_ _1"></span>P Change Logs<span class="_ _1"></span>: <span class="fc1 ls50 ws7">72775</span></div><div class="t m0 x19 h11 y77 ff6 fs9 fc1 sc0 ls51 ws48"> Xilinx Support web page</div><div class="t m0 x25 h14 y78 ff1 fsb fc0 sc0 ls52 ws7">Notes: </div><div class="t m0 x25 h11 y79 ff6 fs9 fc0 sc0 ls53 ws49">1.<span class="_ _18"> </span>For a complete listi<span class="_ _5"></span>ng of supported de<span class="_ _5"></span>vices, see the Viva<span class="_ _5"></span>do IP </div><div class="t m0 x26 h11 y7a ff6 fs9 fc0 sc0 ls54 ws7">catalog. </div><div class="t m0 x25 h11 y7b ff6 fs9 fc0 sc0 ls55 ws4a">2.<span class="_ _18"> </span>For the supported versions of the tools, see the <span class="fc1 ls56 ws7">Xilinx<span class="_"> </span>Des<span class="_ _5"></span>ign<span class="_"> </span> </span></div><div class="t m0 x26 h11 y7c ff6 fs9 fc1 sc0 ls4a ws4b">T<span class="_ _2"></span>ools: Release Notes Guide<span class="fc0 ls1 ws7">.</span></div><div class="c x27 y7d w3 h15"><div class="t m4 x28 h16 y7e ff5 fsc fc2 sc0 ls1 ws7"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c906ebc2d3963da84ceaa/bg5.jpg"><div class="t m0 x2 h6 y6 ff3 fs4 fc0 sc0 ls5 ws5">Discret<span class="_ _1"></span>e Fourier T<span class="_ _2"></span>rans<span class="_ _1"></span>form v4.2<span class="_ _3"> </span>5</div><div class="t m0 x2 h7 y7 ff4 fs4 fc0 sc0 ls6 ws6">PG106 December 10, 2020<span class="_ _4"> </span><span class="fc1 ls7 ws7">www<span class="_ _2"></span>.xil<span class="_ _5"></span>inx.com</span></div><div class="t m0 x29 h17 y7f ff8 fs8 fc0 sc0 ls57 ws7">Chapt<span class="_ _1"></span>er<span class="_"> </span>1</div><div class="t m0 x2 h8 y80 ff4 fs1 fc0 sc0 ls58 ws7">Ov<span class="_ _1"></span>er<span class="_ _5"></span>view</div><div class="t m0 x3 h18 y81 ff3 fsd fc0 sc0 ls59 ws4c">Na<span class="_ _1"></span>vig<span class="_ _1"></span>a<span class="_ _1"></span>ting Cont<span class="_ _1"></span>en<span class="_ _1"></span>t by Design Pr<span class="_ _1"></span>ocess</div><div class="t m0 x3 hd y82 ff6 fs4 fc0 sc0 ls5a ws4d">Xilinx documentation is organize<span class="ls1e ws23">d around a set of standard <span class="_ _1"></span>design processes to help you </span></div><div class="t m0 x3 hd y83 ff6 fs4 fc0 sc0 ls1e ws23">find relevant content for your current development task. This document covers the </div><div class="t m0 x3 hd y84 ff6 fs4 fc0 sc0 ls5b ws4e">following design processes:</div><div class="t m0 x3 he y85 ff6 fs4 fc0 sc0 ls1 ws7">•<span class="_ _19"> </span><span class="ff1 ls5c ws4f">Hardware, IP<span class="_ _1a"></span>, and Plat<span class="ls5d ws50">form Development: <span class="ff6 ls2b ws51">Creating the PL IP blocks for the hardware </span></span></span></div><div class="t m0 x2a hd y86 ff6 fs4 fc0 sc0 ls2b ws52">platform, creating PL kernels, <span class="_ _5"></span>subsystem <span class="ls5e ws53">functional simulation, and evaluating the </span></div><div class="t m0 x2a hd y87 ff6 fs4 fc0 sc0 ls1e ws23">Vivado timing, resource and power closure. Also involves developing the hardware </div><div class="t m0 x2a hd y88 ff6 fs4 fc0 sc0 ls26 ws24">platform for system integration. T<span class="_ _2"></span>o<span class="_ _1"></span>pics in this document that apply to this de<span class="_ _5"></span>sign </div><div class="t m0 x2a hd y89 ff6 fs4 fc0 sc0 ls5f ws54">process include:</div><div class="t m0 x2a hf y8a ff6 fs7 fc0 sc0 ls1 ws7">°</div><div class="t m0 x2b hd y8b ff6 fs4 fc1 sc0 ls5c ws55">P<span class="_ _1"></span>ort Descriptions</div><div class="t m0 x2a hf y8c ff6 fs7 fc0 sc0 ls1 ws7">°</div><div class="t m0 x2b hd y8d ff6 fs4 fc1 sc0 ls5c ws7">Clocking</div><div class="t m0 x2a hf y8e ff6 fs7 fc0 sc0 ls1 ws7">°</div><div class="t m0 x2b hd y8f ff6 fs4 fc1 sc0 ls60 ws7">Re<span class="_ _5"></span>s<span class="_ _5"></span>e<span class="_ _5"></span>t<span class="_ _5"></span>s</div><div class="t m0 x2a hf y90 ff6 fs7 fc0 sc0 ls1 ws7">°</div><div class="t m0 x2b hd y91 ff6 fs4 fc1 sc0 ls1a ws56">Customizing and Generating the Core</div><div class="t m0 x2a hf y92 ff6 fs7 fc0 sc0 ls1 ws7">°</div><div class="t m0 x2b hd y93 ff6 fs4 fc1 sc0 ls61 ws57">C Model</div><div class="t m0 x3 h18 y94 ff3 fsd fc0 sc0 ls62 ws58">Feat<span class="_ _c"></span>u<span class="_ _5"></span>re S<span class="_ _5"></span>u<span class="_ _5"></span>m<span class="_ _5"></span>m<span class="_ _5"></span>a<span class="_ _5"></span>r<span class="_ _5"></span>y</div><div class="t m0 x3 hd y95 ff6 fs4 fc0 sc0 ls2b ws2b">The Discrete Fourier T<span class="_ _2"></span>ransform IP core impl<span class="ls5e ws59">ements forward and inverse <span class="_ _1"></span>DFT<span class="_ _2"></span>s for <span class="_ _1"></span>a wide </span></div><div class="t m0 x3 hd y96 ff6 fs4 fc0 sc0 ls24 ws5a">range of selectable point sizes, including 1296 and 1536 for the 3GPP L<span class="_ _2"></span>TE standard <span class="fc1 ls1b ws7">[Ref<span class="_"> </span>1]<span class="fc0 ls63">. </span></span></div><div class="t m0 x3 hd y97 ff6 fs4 fc0 sc0 ls5c ws55">Additionally supported point sizes range fr<span class="ls1b ws27">om 1440 to 3240 for the 3GPP 5G-New Radio </span></div><div class="t m0 x3 hd y98 ff6 fs4 fc0 sc0 ls1a ws7">standard <span class="fc1 ls1b">[R<span class="_ _1"></span>ef<span class="_"> </span>2]<span class="fc0 ls21 ws5b">. The point size and the transform direction can be changed<span class="_ _5"></span> on a </span></span></div><div class="t m0 x3 hd y99 ff6 fs4 fc0 sc0 ls64 ws5c">frame-by-frame basis. The core supports inpu<span class="ls21 ws5b">t data widths of 8 to 18 bits<span class="_ _5"></span>, in twos </span></div><div class="t m0 x3 hd y9a ff6 fs4 fc0 sc0 ls61 ws5d">complement format. A bit-accurate C model is <span class="ls27 ws5e">de<span class="_ _5"></span>livered with the core<span class="ls5e ws5f"> to support software </span></span></div><div class="t m0 x3 hd y9b ff6 fs4 fc0 sc0 ls2b ws7">simulation. </div><div class="c x5 y25 w2 ha"><div class="t m1 x6 hb y26 ff5 fs5 fc2 sc0 ls1 ws7"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>