<html xmlns="http://www.w3.org/1999/xhtml"><head><meta charset="utf-8"><meta name="generator" content="pdf2htmlEX"><meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/base.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/10763053/raw.css"><script src="https://csdnimg.cn/release/download_crawler_static/js/compatibility.min.js"></script><script src="https://csdnimg.cn/release/download_crawler_static/js/pdf2htmlEX.min.js"></script><script>try{pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({});}catch(e){}</script><title></title></head><body><div id="sidebar" style="display: none"><div id="outline"></div></div><div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/10763053/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Copyright ©<span class="_"> </span>2007 ARM Limited. All rights reserved.</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">ARM DDI 0424A</div><div class="t m0 x3 h3 y3 ff1 fs1 fc0 sc0 ls2 ws2">Pr<span class="_ _0"></span>imeCell</div><div class="t m0 x4 h4 y4 ff1 fs2 fc0 sc0 ls3 ws2">®</div><div class="t m0 x5 h3 y3 ff1 fs1 fc0 sc0 ls4 ws3"> DMA Controller (PL330)</div><div class="t m0 x6 h5 y5 ff2 fs3 fc0 sc0 ls5 ws2">Revisi<span class="_ _1"></span>on: r0p0</div><div class="t m0 x7 h6 y6 ff2 fs4 fc0 sc0 ls3 ws4">T<span class="_ _2"></span>echnical Ref<span class="_ _1"></span>erence Man<span class="_ _1"></span>ual</div></div><div class="pi" data-data='{"ctm":[1.777778,0.000000,0.000000,1.777778,0.000000,0.000000]}'></div></div></body></html>
<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/10763053/bg2.jpg"><div class="t m0 x8 h2 y7 ff3 fs0 fc0 sc0 ls3 ws2"> </div><div class="t m0 x8 h2 y8 ff1 fs0 fc0 sc0 ls6 ws2">ii<span class="_ _3"> </span><span class="ff3 ls0 ws0">Copyright ©<span class="_"> </span>2007 ARM Limited. All rights reserved.<span class="_ _4"> </span></span><span class="ls7 ws5">ARM DDI 0424A</span></div><div class="t m0 x9 h7 y9 ff2 fs5 fc0 sc0 ls3 ws6">PrimeCell DMA Controller (PL330)</div><div class="t m0 x9 h8 ya ff2 fs6 fc0 sc0 ls8 ws7">T<span class="_ _5"></span>echnical<span class="_ _1"></span> Reference <span class="_ _1"></span>Manual</div><div class="t m0 x9 h9 yb ff4 fs6 fc0 sc0 ls9 ws8">Copyright ©<span class="_"> </span>2007 A<span class="_ _0"></span>RM Limited. All right<span class="_ _0"></span>s reserv<span class="_ _1"></span>ed.</div><div class="t m0 x9 h2 yc ff2 fs0 fc0 sc0 lsa ws9">Release Information</div><div class="t m0 x9 ha yd ff4 fs0 fc0 sc0 lsb ws2">The <span class="ff5 lsc wsa">Change histor<span class="_ _0"></span>y</span><span class="lsd wsb"> table lists the <span class="_ _1"></span>changes made to this manual.</span></div><div class="t m0 x9 h2 ye ff2 fs0 fc0 sc0 ls3 wsc">Proprietary Notice</div><div class="t m0 x9 ha yf ff4 fs0 fc0 sc0 lse wsd">W<span class="_ _5"></span>ords and logos mar<span class="_ _1"></span>ked with </div><div class="t m0 xa hb y10 ff4 fs7 fc0 sc0 ls3 ws2">®</div><div class="t m0 xb ha y11 ff4 fs0 fc0 sc0 lsf wse"> or </div><div class="t m0 xc hb y10 ff4 fs7 fc0 sc0 ls3 ws2">™</div><div class="t m0 xd ha y11 ff4 fs0 fc0 sc0 ls10 wsf"> are registered trademarks or tradem<span class="ls11 ws10">arks of ARM Limited in the EU and </span></div><div class="t m0 x9 ha y12 ff4 fs0 fc0 sc0 lsd ws11">other countries, except as otherwise stated below in<span class="ls12 ws12"> this prop<span class="_ _0"></span>rietary notice. Other brand<span class="_ _0"></span>s and names </span></div><div class="t m0 x9 ha y13 ff4 fs0 fc0 sc0 ls12 ws12">mentioned her<span class="_ _0"></span>ein may be the tradem<span class="ls13 ws13">ar<span class="_ _0"></span>ks of their respectiv<span class="_ _1"></span>e o<span class="_ _1"></span>wners.</span></div><div class="t m0 x9 ha y14 ff4 fs0 fc0 sc0 ls14 ws14">Neither the whole nor any par<span class="_ _0"></span>t of the information cont<span class="ls15 ws15">ained in, or the product descr<span class="_ _1"></span>ibed in, this document </span></div><div class="t m0 x9 ha y15 ff4 fs0 fc0 sc0 ls3 ws16">may be adapted or reproduced in any material form ex<span class="ls16 ws17">cept <span class="_ _0"></span>with the prior written permission of the copyright </span></div><div class="t m0 x9 ha y16 ff4 fs0 fc0 sc0 ls17 ws2">holder<span class="_ _1"></span>.</div><div class="t m0 x9 ha y17 ff4 fs0 fc0 sc0 ls18 ws18">The product described<span class="_ _1"></span> in this document <span class="_ _1"></span>is subject <span class="lsd wsb">to continuous<span class="_ _1"></span> dev<span class="_ _1"></span>elopmen<span class="ls13 ws13">ts and improvements. All </span></span></div><div class="t m0 x9 ha y18 ff4 fs0 fc0 sc0 ls19 ws19">particulars of the product and its use contained in this<span class="_ _1"></span> document are giv<span class="_ _1"></span>en by AR<span class="_ _1"></span>M in good faith. Ho<span class="_ _1"></span>we<span class="_ _1"></span>ver<span class="_ _5"></span>, </div><div class="t m0 x9 ha y19 ff4 fs0 fc0 sc0 ls1a ws1a">all warranties implied or expressed,<span class="_ _1"></span><span class="ls1b ws1b"> including but not limit<span class="lsd wsb">ed to implied warrantie<span class="ls14 ws14">s of merchantability<span class="_ _5"></span>,<span class="_ _0"></span> or </span></span></span></div><div class="t m0 x9 ha y1a ff4 fs0 fc0 sc0 ls7 ws1c">fitness for purpose, are excluded.</div><div class="t m0 x9 ha y1b ff4 fs0 fc0 sc0 ls1c ws1d">This document is intended only to a<span class="ls3 ws1e">ssist the reade<span class="_ _0"></span>r in the use <span class="_ _1"></span>of the pr<span class="ls13">oduct. ARM Limited shall not be liable </span></span></div><div class="t m0 x9 ha y1c ff4 fs0 fc0 sc0 ls1d ws1f">for any loss or<span class="_ _1"></span> damage arising from the use of any info<span class="_ _1"></span>rmation in this document, or an<span class="_ _1"></span>y error or omission in </div><div class="t m0 x9 ha y1d ff4 fs0 fc0 sc0 ls1e ws20">such information, or an<span class="_ _1"></span>y in<span class="ls14 ws14">correct use of the product.</span></div><div class="t m0 x9 ha y1e ff4 fs0 fc0 sc0 ls1 ws21">Where the term ARM is used it means “ARM or<span class="lse ws22"> any of its subsidiaries as appropriate”.</span></div><div class="t m0 x9 h2 y1f ff2 fs0 fc0 sc0 lsd ws2">Confidentiality Status</div><div class="t m0 x9 ha y20 ff4 fs0 fc0 sc0 lsa ws23">This document is Non-Confidential. <span class="ls18 ws24">The right to use, cop<span class="_ _1"></span>y and disclose this document may be subject to </span></div><div class="t m0 x9 ha y21 ff4 fs0 fc0 sc0 ls1f ws25">license restrictions in acco<span class="ls3 ws26">rdance with the <span class="_ _0"></span>terms of th<span class="ls14 ws14">e agreement entered into by<span class="ls16 ws27"> ARM and the party that </span></span></span></div><div class="t m0 x9 ha y22 ff4 fs0 fc0 sc0 ls13 ws13">ARM delivered this document to.</div><div class="t m0 x9 h2 y23 ff2 fs0 fc0 sc0 ls20 ws28">Product Status</div><div class="t m0 x9 ha y24 ff4 fs0 fc0 sc0 ls1 ws21">The information in this do<span class="ls1f ws29">cument is final, that is for a <span class="_ _0"></span>de<span class="_ _1"></span>veloped product.</span></div><div class="t m0 x9 h2 y25 ff2 fs0 fc0 sc0 ls1f ws2a">W<span class="_ _1"></span>eb Address</div><div class="t m1 x9 hc y26 ff6 fs8 fc0 sc0 ls3 ws2">http://w<span class="_ _1"></span>ww.arm.co<span class="_ _1"></span>m</div><div class="t m0 xe hd y27 ff2 fs9 fc0 sc0 ls21 ws2b">Change history</div><div class="t m0 xa hd y28 ff2 fs9 fc0 sc0 ls22 ws2">Date<span class="_ _6"> </span>Issue<span class="_ _7"> </span>Confidentiality<span class="_ _8"> </span>Change</div><div class="t m0 xa he y29 ff4 fs9 fc0 sc0 ls23 ws2c">19 December 2007<span class="_ _9"> </span>A<span class="_ _a"> </span>Non-Confidential<span class="_ _9"> </span>Fi<span class="ls24 ws2d">rst is<span class="_ _1"></span>sue for the r0p0 release</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.777778,0.000000,0.000000,1.777778,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/10763053/bg3.jpg"><div class="t m0 xf h2 y1 ff1 fs0 fc0 sc0 ls1 ws1">ARM DDI 0424A<span class="_ _4"> </span><span class="ff3 ls0 ws0">Copyright ©<span class="_"> </span>2007 ARM Limited. All rights reserved.<span class="_ _b"> </span></span><span class="ls25 ws2">iii</span></div><div class="t m0 xf hf y2a ff1 fsa fc0 sc0 ls26 ws2">Contents</div><div class="t m0 xf hf y2b ff2 fsa fc0 sc0 ls27 ws2e">PrimeCell DMA Contr<span class="_ _5"></span>oller (PL330) T<span class="_ _2"></span>echnical </div><div class="t m0 xf hf y2c ff2 fsa fc0 sc0 ls28 ws2f">Reference Man<span class="_ _5"></span>u<span class="_ _0"></span>al</div><div class="t m0 x10 h10 y2d ff2 fsb fc0 sc0 ls29 ws2">Preface</div><div class="t m0 x4 h11 y2e ff1 fsc fc0 sc0 ls2a ws30">About this manual <span class="_ _c"> </span>...............<span class="ls2b ws2">........................................................<span class="_ _1"></span>..............<span class="ls2c ws31">.....<span class="_ _c"> </span> x</span></span></div><div class="t m0 x4 h11 y2f ff1 fsc fc0 sc0 ls2d ws32">Feedback ...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>....... <span class="_ _d"></span>xv</div><div class="t m0 x3 h10 y30 ff2 fsb fc0 sc0 ls2e ws2">Chapter<span class="_"> </span>1<span class="_ _e"> </span>Introduction</div><div class="t m0 x10 h11 y31 ff1 fsc fc0 sc0 ls2f ws33">1.1<span class="_ _f"> </span>About the DMAC <span class="_ _10"> </span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _11"></span> 1-2</div><div class="t m0 x10 h11 y32 ff1 fsc fc0 sc0 ls2f ws34">1.2<span class="_ _f"> </span>Terminology .......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _11"></span> <span class="_ _d"></span>1-5</div><div class="t m0 x3 h10 y33 ff2 fsb fc0 sc0 ls30 ws35">Chapter<span class="_"> </span>2<span class="_ _e"> </span>Functional Overview</div><div class="t m0 x10 h11 y34 ff1 fsc fc0 sc0 ls31 ws36">2.1<span class="_ _f"> </span>Overview ...<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="_ _11"> </span> <span class="_ _12"></span>2-2</div><div class="t m0 x10 h11 y35 ff1 fsc fc0 sc0 ls32 ws37">2.2<span class="_ _f"> </span>DMAC interfaces <span class="_ _11"></span>........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _11"></span> 2-4</div><div class="t m0 x10 h11 y36 ff1 fsc fc0 sc0 ls32 ws38">2.3<span class="_ _f"> </span>Operating states <span class="_ _0"></span>..................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _11"></span> 2-10</div><div class="t m0 x10 h11 y37 ff1 fsc fc0 sc0 ls33 ws39">2.4<span class="_ _f"> </span>Initializing the DMAC <span class="_ _0"></span>.............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>.........<span class="_ _11"></span> 2-14</div><div class="t m0 x10 h11 y38 ff1 fsc fc0 sc0 ls34 ws3a">2.5<span class="_ _f"> </span>Using the APB slave interfac<span class="ls35 ws3b">es ..............<span class="ls2b ws2">..............<span class="ls36">...........<span class="ls37">............<span class="ls38 ws3c">..............<span class="_ _11"></span> 2-16</span></span></span></span></span></div><div class="t m0 x10 h11 y39 ff1 fsc fc0 sc0 ls39 ws3d">2.6<span class="_ _f"> </span>Peripheral request interface <span class="_ _11"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _11"></span> 2-18</div><div class="t m0 x10 h11 y3a ff1 fsc fc0 sc0 ls2c ws3e">2.7<span class="_ _f"> </span>Using events and interrupts <span class="_ _c"> </span>..............<span class="_ _1"></span>.....<span class="ls2f ws33">......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...<span class="_ _11"> </span> 2-23</span></div><div class="t m0 x10 h11 y3b ff1 fsc fc0 sc0 ls2f ws3f">2.8<span class="_ _f"> </span>Aborts ...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.........<span class="_ _11"></span> <span class="_ _5"></span>2-25</div><div class="t m0 x10 h11 y3c ff1 fsc fc0 sc0 ls32 ws37">2.9<span class="_ _f"> </span>Security usage <span class="_ _c"> </span>......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _11"></span> 2-29</div><div class="t m0 x10 h11 y3d ff1 fsc fc0 sc0 ls3a ws40">2.10<span class="_ _13"> </span>Constraints and limitations of use <span class="_ _10"> </span>..........<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>......<span class="_ _11"></span> 2-34</div><div class="t m0 x10 h11 y3e ff1 fsc fc0 sc0 ls3a ws41">2.11<span class="_ _13"> </span>Programming restrictions <span class="_ _10"> </span>............<span class="_ _1"></span>........<span class="ls2f ws33">...<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.........<span class="_ _11"></span> 2-35</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.777778,0.000000,0.000000,1.777778,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/10763053/bg4.jpg"><div class="t m0 x8 h2 y7 ff3 fs0 fc0 sc0 ls10 ws2">Contents</div><div class="t m0 x8 h2 y8 ff1 fs0 fc0 sc0 ls6 ws2">iv<span class="_ _14"> </span><span class="ff3 ls0 ws0">Copyright ©<span class="_"> </span>2007 ARM Limited. All rights reserved.<span class="_ _4"> </span></span><span class="ls7 ws5">ARM DDI 0424A</span></div><div class="t m0 x11 h10 y3f ff2 fsb fc0 sc0 ls2e ws42">Chapter<span class="_"> </span>3<span class="_ _e"> </span>Programmers Model</div><div class="t m0 x9 h11 y40 ff1 fsc fc0 sc0 ls35 ws43">3.1<span class="_ _f"> </span>About the programmers mode<span class="ls31 ws44">l .............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="_ _15"> </span> <span class="_ _12"></span>3-2</span></div><div class="t m0 x9 h11 y41 ff1 fsc fc0 sc0 ls2c ws31">3.2<span class="_ _f"> </span>DMAC Register summary <span class="_ _0"></span>.....................<span class="_ _1"></span>...<span class="ls3b ws45">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span>...<span class="_"> </span> 3-4</span></div><div class="t m0 x9 h11 y42 ff1 fsc fc0 sc0 ls3c ws46">3.3<span class="_ _f"> </span>DMAC Register descriptions<span class="_ _1"></span> <span class="_ _c"> </span>................<span class="ls2f ws33">......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>....<span class="_"> </span> 3-11</span></div><div class="t m0 x11 h10 y43 ff2 fsb fc0 sc0 ls3d ws2">Chapter<span class="_"> </span>4<span class="_ _e"> </span>Instruction Set</div><div class="t m0 x9 h11 y44 ff1 fsc fc0 sc0 ls39 ws3d">4.1<span class="_ _f"> </span>Instruction syntax conventions <span class="_"> </span>.....<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>...<span class="_"> </span> 4-2</div><div class="t m0 x9 h11 y45 ff1 fsc fc0 sc0 ls3e ws47">4.2<span class="_ _f"> </span>Instruction set summary <span class="_"> </span>.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>...<span class="_"> </span> 4-3</div><div class="t m0 x9 h11 y46 ff1 fsc fc0 sc0 ls2f ws48">4.3<span class="_ _f"> </span>Instructions ..........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...<span class="_ _15"> </span> <span class="_ _d"></span>4-5</div><div class="t m0 x9 h11 y47 ff1 fsc fc0 sc0 ls3f ws49">4.4<span class="_ _f"> </span>Assembler directives <span class="_"> </span>...<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1"></span><span class="ls2f ws33">..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..........<span class="_ _c"> </span> 4-25</span></div><div class="t m0 x11 h10 y48 ff2 fsb fc0 sc0 ls3d ws2">Appendix<span class="_"> </span>A<span class="_ _16"> </span>Signal Descriptions</div><div class="t m0 x9 h11 y49 ff1 fsc fc0 sc0 ls40 ws4a">A.1<span class="_ _17"> </span>Clocks and resets <span class="_ _11"> </span>..<span class="ls2b ws2">......................................................................<span class="ls37">............<span class="ls41 ws4b">...<span class="_ _10"> </span> A-2</span></span></span></div><div class="t m0 x9 h11 y4a ff1 fsc fc0 sc0 ls42 ws4c">A.2<span class="_ _17"> </span>AXI signals <span class="_ _0"></span>.............<span class="ls2b ws2">..............<span class="_ _1"></span>........................................................<span class="ls37">............<span class="_ _1"></span><span class="ls43 ws4d">...<span class="_ _10"> </span> A-3</span></span></span></div><div class="t m0 x9 h11 y4b ff1 fsc fc0 sc0 ls44 ws4e">A.3<span class="_ _17"> </span>APB signals <span class="_ _18"> </span>...........<span class="ls2b ws2">........................................................<span class="_ _1"></span>..............<span class="ls37">............<span class="ls41 ws4b">...<span class="_ _10"> </span> A-7</span></span></span></div><div class="t m0 x9 h11 y4c ff1 fsc fc0 sc0 ls45 ws4f">A.4<span class="_ _17"> </span>Peripheral request interfac<span class="ls40 ws50">e ..............<span class="ls2b ws2">..........................................<span class="ls37">............<span class="ls43 ws4d">...<span class="_ _10"> </span> A-9</span></span></span></span></div><div class="t m0 x9 h11 y4d ff1 fsc fc0 sc0 ls3e ws51">A.5<span class="_ _17"> </span>Interrupt signals <span class="_ _11"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>................<span class="_ _1"></span>.............<span class="_ _11"> </span> A-11</div><div class="t m0 x9 h11 y4e ff1 fsc fc0 sc0 ls46 ws52">A.6<span class="_ _17"> </span>Tie-off signals <span class="_ _18"> </span>......<span class="ls2b ws2">......................................................................<span class="ls36">...........<span class="ls47 ws53">....<span class="_ _10"> </span> A-12</span></span></span></div><div class="t m0 x9 h10 y4f ff2 fsb fc0 sc0 ls48 ws2">Glossary</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/10763053/bg5.jpg"><div class="t m0 xf h2 y1 ff1 fs0 fc0 sc0 ls1 ws1">ARM DDI 0424A<span class="_ _4"> </span><span class="ff3 ls0 ws0">Copyright ©<span class="_"> </span>2007 ARM Limited. All rights reserved.<span class="_ _19"> </span></span><span class="ls3 ws2">v</span></div><div class="t m0 xf hf y2a ff1 fsa fc0 sc0 ls27 ws54">List of T<span class="_ _1a"></span>ab<span class="_ _1"></span>les</div><div class="t m0 xf hf y2b ff2 fsa fc0 sc0 ls27 ws2e">PrimeCell DMA Contr<span class="_ _5"></span>oller (PL330) T<span class="_ _2"></span>echnical </div><div class="t m0 xf hf y2c ff2 fsa fc0 sc0 ls28 ws2f">Reference Man<span class="_ _5"></span>u<span class="_ _0"></span>al</div><div class="t m0 x10 h11 y50 ff1 fsc fc0 sc0 ls42 ws55">Change history <span class="_ _10"> </span>..............<span class="ls2b ws2">........................................................<span class="ls36">......................<span class="_ _1"></span><span class="ls37">............<span class="ls42 ws55">...... i</span><span class="ls3">i</span></span></span></span></div><div class="t m0 x12 h11 y51 ff1 fsc fc0 sc0 ls2b ws56">Table<span class="_"> </span>2-1<span class="_ _1b"> </span>AXI characteristics for a DMA transfer <span class="_ _10"> </span>.........<span class="ls31 ws57">.....<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="_ _11"></span> 2-8</span></div><div class="t m0 x12 h11 y52 ff1 fsc fc0 sc0 ls41 ws4b">Table<span class="_"> </span>2-2<span class="_ _1b"> </span>Handshake rules <span class="_ _c"> </span>...<span class="ls2b ws2">........................................................<span class="_ _1"></span>..............<span class="ls36">......................<span class="ls3f ws58">......<span class="_ _11"></span> 2</span><span class="ls49">-19</span></span></span></div><div class="t m0 x12 h11 y53 ff1 fsc fc0 sc0 ls47 ws59">Table<span class="_"> </span>3-1<span class="_ _1b"> </span>DMAC Control Register su<span class="ls2d ws5a">mmary ................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _11"></span> <span class="_ _2"></span>3-4</span></div><div class="t m0 x12 h11 y54 ff1 fsc fc0 sc0 ls47 ws59">Table<span class="_"> </span>3-2<span class="_ _1b"> </span>DMA channel thread status register summary<span class="ls31 ws5b"> ................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _11"></span> <span class="_ _12"></span>3-6</span></div><div class="t m0 x12 h11 y55 ff1 fsc fc0 sc0 ls4a ws5c">Table<span class="_"> </span>3-3<span class="_ _1b"> </span>AXI status and loop counte<span class="_ _0"></span>r register summar<span class="ls3 ws5d">y ..........<span class="ls2b ws2">..............<span class="_ _1"></span>............................<span class="ls4b ws5e">.....<span class="_ _11"></span> 3-7</span></span></span></div><div class="t m0 x12 h11 y56 ff1 fsc fc0 sc0 ls3c ws46">Table<span class="_"> </span>3-4<span class="_ _1b"> </span>DMAC Debug Register summary <span class="_ _1c"></span>.................<span class="_ _1"></span><span class="ls31 ws57">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1c"></span> 3-9</span></div><div class="t m0 x12 h11 y57 ff1 fsc fc0 sc0 ls46 ws5f">Table<span class="_"> </span>3-5<span class="_ _1b"> </span>DMAC Configuration Regi<span class="_ _0"></span>ster summary <span class="_ _10"> </span>......<span class="ls31 ws57">.....<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="_ _11"> </span> 3-9</span></div><div class="t m0 x12 h11 y58 ff1 fsc fc0 sc0 ls4c ws60">Table<span class="_"> </span>3-6<span class="_ _1b"> </span>Pe<span class="_ _0"></span>ripheral and PrimeCell <span class="ls47 ws53">Identification Register summary <span class="_ _10"> </span><span class="ls36 ws2">...........<span class="ls37">............<span class="ls38 ws3c">..............<span class="_ _1c"></span> 3-10</span></span></span></span></div><div class="t m0 x12 h11 y59 ff1 fsc fc0 sc0 ls32 ws38">Table<span class="_"> </span>3-7<span class="_ _1b"> </span>DS Register bit assignments <span class="_ _1c"></span>..................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.........<span class="_ _11"></span> 3-11</div><div class="t m0 x12 h11 y5a ff1 fsc fc0 sc0 ls32 ws38">Table<span class="_"> </span>3-8<span class="_ _1b"> </span>DPC Register bit assignments <span class="_ _c"> </span>.......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1c"></span> 3-13</div><div class="t m0 x12 h11 y5b ff1 fsc fc0 sc0 ls4d ws61">Table<span class="_"> </span>3-9<span class="_ _1b"> </span>INTEN Register bit assignments <span class="_ _10"> </span>............<span class="_ _1"></span>...<span class="ls2d ws62">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1c"></span> 3-14</span></div><div class="t m0 x12 h11 y5c ff1 fsc fc0 sc0 ls3e ws51">Table<span class="_"> </span>3-10<span class="_ _1d"> </span>ES Register b<span class="_ _1"></span>it assignment<span class="ls2d ws63">s ....<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1c"></span> <span class="_ _12"></span>3-15</span></div><div class="t m0 x12 h11 y5d ff1 fsc fc0 sc0 ls47 ws53">Table<span class="_"> </span>3-11<span class="_ _1e"> </span>INTSTATUS Register bit assignments <span class="_ _10"> </span>......<span class="ls2d ws62">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span>..............<span class="_ _1c"></span> 3-16</span></div><div class="t m0 x12 h11 y5e ff1 fsc fc0 sc0 ls4e ws64">Table<span class="_"> </span>3-12<span class="_ _1e"> </span>INTCLR Register bit assi<span class="ls32 ws65">gnments .....................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1c"></span> <span class="_ _5"></span>3-17</span></div><div class="t m0 x12 h11 y5f ff1 fsc fc0 sc0 ls4f ws66">Table<span class="_"> </span>3-13<span class="_ _1d"> </span>FSM Register bit assignments <span class="_"> </span>.<span class="_ _1"></span>..............<span class="_ _1"></span><span class="ls2d ws62">...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1c"></span> 3-18</span></div><div class="t m0 x12 h11 y60 ff1 fsc fc0 sc0 ls4f ws67">Table<span class="_"> </span>3-14<span class="_ _1d"> </span>FSC Register bit assignments <span class="_ _0"></span>.............<span class="_ _1"></span>...<span class="ls2d ws62">.........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>...<span class="_ _11"> </span> 3-19</span></div><div class="t m0 x12 h11 y61 ff1 fsc fc0 sc0 ls2d ws62">Table<span class="_"> </span>3-1<span class="_ _1"></span>5<span class="_ _1e"> </span>FTM Regist<span class="_ _1"></span>er bit assignm<span class="ws68">ents .<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1c"></span> <span class="_ _1a"></span>3-20</span></div><div class="t m0 x12 h11 y62 ff1 fsc fc0 sc0 ls33 ws69">Table<span class="_"> </span>3-16<span class="_ _1d"> </span>FTC Register bit assignments <span class="_ _11"> </span>................<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>......<span class="_ _11"></span> 3-22</div><div class="t m0 x12 h11 y63 ff1 fsc fc0 sc0 ls50 ws6a">Table<span class="_"> </span>3-17<span class="_ _1e"> </span>CSn Register bit assignmen<span class="ls2d ws5a">ts ...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>...<span class="_ _11"> </span> <span class="_ _2"></span>3-25</span></div><div class="t m0 x12 h11 y64 ff1 fsc fc0 sc0 ls4b ws5e">Table<span class="_"> </span>3-18<span class="_ _1d"> </span>CPCn Register bit assignments <span class="_ _c"> </span>..........<span class="_ _1"></span>......<span class="ls2d ws62">......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1c"></span> 3-27</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div 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