U盘制作资料

  • n0_576111
    了解作者
  • 399.3KB
    文件大小
  • rar
    文件格式
  • 0
    收藏次数
  • VIP专享
    资源类型
  • 0
    下载次数
  • 2022-06-11 13:48
    上传日期
采用IC1114-F48LQ制作USB存储器,附有电路原理图,以及IC1114-F48LQ资料等。
u盘制作资料.rar
  • 新建文件夹
  • flash_disk_schmatic_v34.opj
    1.1KB
  • FLASH_DISK_SCHMATIC_V34.DSN
    100KB
  • FLASH_DISK_SCHMATIC_V34.pdf
    23.8KB
  • FlashDiskV17A(WriteProtect).HEX
    37.1KB
  • IC1114-F48LQ Promotion v2.1.pdf
    247.2KB
  • FlashDiskV17A(No_WriteProtect).HEX
    37.1KB
  • IC1114 Datasheet V1.pdf
    704.3KB
  • Ic17-2.job
    41.4KB
内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"><head><meta charset="utf-8"><meta name="generator" content="pdf2htmlEX"><meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/base.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/7818373/raw.css"><script src="https://csdnimg.cn/release/download_crawler_static/js/compatibility.min.js"></script><script src="https://csdnimg.cn/release/download_crawler_static/js/pdf2htmlEX.min.js"></script><script>try{pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({});}catch(e){}</script><title></title></head><body><div id="sidebar" style="display: none"><div id="outline"></div></div><div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/7818373/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">IC1<span class="_ _0"></span>1<span class="_ _0"></span>14-F48<span class="_ _1"></span>LQ</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0"> </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls2 ws0"> <span class="_ _2"></span> </div><div class="t m0 x1 h4 y4 ff1 fs2 fc0 sc0 ls1 ws0"> </div><div class="t m0 x2 h4 y5 ff1 fs2 fc0 sc0 ls1 ws0"> </div><div class="t m0 x1 h5 y6 ff2 fs3 fc0 sc0 ls3 ws1">Integrated Cir<span class="_ _1"></span>cuit Solution Inc.<span class="ff1 ls4 ws2"> <span class="_ _3"> </span> <span class="_ _4"> </span> <span class="_ _5"> </span>V<span class="_ _6"></span>ersion <span class="_ _7"></span>1.0 </span></div><div class="t m0 x3 h6 y7 ff1 fs4 fc0 sc0 ls5 ws0">1 </div><div class="t m0 x1 h7 y8 ff3 fs3 fc0 sc0 ls6 ws0">1.<span class="ff4 ls1"> <span class="_ _8"> </span></span><span class="ls7">FEATURE<span class="_ _2"></span>S </span></div><div class="t m0 x1 h8 y9 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls8 ws3">High speed 8-bit micro<span class="_ _2"></span>-control<span class="_ _1"></span>ler<span class="_ _2"></span> with 4 system clocks </span></span></div><div class="t m0 x4 h6 ya ff1 fs4 fc0 sc0 ls9 ws4">per machine cycle </div><div class="t m0 x1 h8 yb ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls8 ws3">Instruction-set compatible with MCS-51 </span></span></div><div class="t m0 x1 h8 yc ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lsa ws5">Emb<span class="_ _1"></span>edded 32K-by<span class="_ _1"></span>te progr<span class="_ _1"></span>am FL<span class="_ _1"></span>ASH ROM for </span></span></div><div class="t m0 x4 h6 yd ff1 fs4 fc0 sc0 lsb ws6">product<span class="_ _1"></span> quick de<span class="_ _1"></span>livery<span class="_ _1"></span>. In Sy<span class="_ _1"></span>stem Programm<span class="_ _1"></span>ing, IS<span class="_ _1"></span>P is </div><div class="t m0 x4 h6 ye ff1 fs4 fc0 sc0 lsa ws5">suppor<span class="_ _1"></span>ted by<span class="_ _1"></span> either USB<span class="_ _1"></span> or I2C port. </div><div class="t m0 x1 h8 yf ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lsc ws7">Built i<span class="_ _1"></span>n fixed add<span class="_ _1"></span>ress 256 by<span class="_ _1"></span>tes data<span class="_ _1"></span> RAM. </span></span></div><div class="t m0 x1 h8 y10 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lsc ws7">Built i<span class="_ _1"></span>n float<span class="_ _1"></span>ing addres<span class="_ _1"></span>s 4608 by<span class="_ _1"></span>tes data RAM </span></span></div><div class="t m0 x1 h8 y11 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lsd ws8">Extra 1K bytes CPU d<span class="_ _2"></span>ata RAM space available by </span></span></div><div class="t m0 x4 h6 y12 ff1 fs4 fc0 sc0 lse ws9">disab<span class="_ _1"></span>le central c<span class="_ _1"></span>ontrol<span class="_ _1"></span> block f<span class="_ _1"></span>unction. </div><div class="t m0 x1 h8 y13 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lsf wsa">Sy<span class="_ _1"></span>stem powe<span class="_ _1"></span>r sav<span class="_ _1"></span>ing mode<span class="_ _1"></span> ready<span class="_ _1"></span>, idle<span class="_ _1"></span> &amp; powe<span class="_ _1"></span>r dow<span class="_ _1"></span>n </span></span></div><div class="t m0 x4 h6 y14 ff1 fs4 fc0 sc0 ls5 ws0">modes.<span class="_ _1"></span> </div><div class="t m0 x1 h8 y15 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls10 wsb">Three<span class="_ _1"></span> programmab<span class="_ _1"></span>le 16-<span class="_ _1"></span>bit timer<span class="_ _1"></span>/counter a<span class="_ _1"></span>nd </span></span></div><div class="t m0 x4 h6 y16 ff1 fs4 fc0 sc0 ls11 wsc">watchd<span class="_ _1"></span>og t<span class="_ _1"></span>imer. </div><div class="t m0 x1 h8 y17 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls12 wsd">Complia<span class="_ _1"></span>nt wi<span class="_ _1"></span>th USB Spec<span class="_ _1"></span>ificat<span class="_ _1"></span>ion Rev.1.<span class="_ _1"></span>1 suppo<span class="_ _1"></span>rts </span></span></div><div class="t m0 x4 h6 y18 ff1 fs4 fc0 sc0 ls13 wse">full sp<span class="_ _2"></span>eed (12Mbits/sec), one d<span class="_ _2"></span>evice address <span class="_ _2"></span>and four </div><div class="t m0 x5 h6 y19 ff1 fs4 fc0 sc0 ls5 wsf">endpo<span class="_ _1"></span>ints. (In<span class="_ _1"></span>cludi<span class="_ _1"></span>ng contro<span class="_ _1"></span>l, interr<span class="_ _1"></span>upt, bu<span class="_ _1"></span>lk in and </div><div class="t m0 x5 h6 ya ff1 fs4 fc0 sc0 ls14 ws10">bul<span class="_ _2"></span>k out e<span class="_ _2"></span>ndpoi<span class="_ _2"></span>nts) </div><div class="t m0 x6 h8 yb ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lsb ws6">Built i<span class="_ _1"></span>n ICSI in-<span class="_ _1"></span>house b<span class="_ _1"></span>i-direc<span class="_ _1"></span>tional para<span class="_ _1"></span>llel por<span class="_ _1"></span>t for </span></span></div><div class="t m0 x5 h6 y1a ff1 fs4 fc0 sc0 ls15 ws11">quick data tr<span class="_ _2"></span>ansfer. Both master and slave modes are </div><div class="t m0 x5 h6 yd ff1 fs4 fc0 sc0 ls16 ws0">supp<span class="_ _2"></span>orted<span class="_ _2"></span>. </div><div class="t m0 x6 h8 y1b ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls17 ws12">Master/Slav<span class="_ _1"></span>e IIC and UART/RS-232 i<span class="_ _1"></span>nterface for </span></span></div><div class="t m0 x5 h6 y1c ff1 fs4 fc0 sc0 ls18 ws13">external device <span class="_ _2"></span>commun<span class="_ _1"></span>ication. </div><div class="t m0 x6 h8 y1d ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls19 ws14">Smart Media<span class="_ _1"></span> Card/NAND<span class="_ _1"></span> type flash c<span class="_ _1"></span>hip interface<span class="_ _1"></span> </span></span></div><div class="t m0 x5 h6 y1e ff1 fs4 fc0 sc0 ls13 ws15">complies with Smart Media S<span class="_ _1"></span>peci<span class="_ _2"></span>fica<span class="_ _1"></span>tion Rev.1.1 and </div><div class="t m0 x5 h6 y1f ff1 fs4 fc0 sc0 ls1a ws16">Smart Media Identif<span class="_ _2"></span>y Number Specification Version </div><div class="t m0 x5 h6 y20 ff1 fs4 fc0 sc0 ls5 ws0">1.1 </div><div class="t m0 x6 h8 y21 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 lse ws9">Built-<span class="_ _1"></span>in hardwa<span class="_ _1"></span>re EC<span class="_ _1"></span>C (Error C<span class="_ _1"></span>orrectio<span class="_ _1"></span>n Code) c<span class="_ _1"></span>heck </span></span></div><div class="t m0 x5 h6 y22 ff1 fs4 fc0 sc0 ls1b ws17">for Smart Media Card/NAND ty<span class="_ _1"></span>pe flash chip<span class="_ _2"></span>. </div><div class="t m0 x6 h8 y23 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls10 ws10">3.0~3.<span class="_ _1"></span>6V supp<span class="_ _1"></span>ly.<span class="_ _1"></span> </span></span></div><div class="t m0 x6 h8 y17 ff5 fs4 fc0 sc0 ls1 ws0">&#8722;<span class="ff6"> <span class="_ _9"> </span><span class="ff1 ls15 ws11">48LQFP packages is <span class="_ _2"></span>availab<span class="_ _1"></span>l<span class="_ _2"></span>e. </span></span></div><div class="t m0 x1 h5 y24 ff1 fs3 fc0 sc0 ls1 ws0"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div></body></html>
评论
    相关推荐