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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/638f674197bc301588149cdc/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">1 of 125</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1"> </div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls2 ws2">GS2972 3G/HD/SD-SDI Serializer with Complete </div><div class="t m0 x3 h2 y3 ff1 fs0 fc0 sc0 ls3 ws3">SMPTE Audio & Video Support</div><div class="t m0 x3 h2 y4 ff1 fs0 fc0 sc0 ls1 ws4">Final Data Sheet<span class="_ _0"> </span>Rev. 9</div><div class="t m0 x3 h2 y5 ff1 fs0 fc0 sc0 ls4 ws5">GENDOC-047479<span class="_ _1"> </span>September 2013</div><div class="t m0 x4 h3 y6 ff2 fs1 fc0 sc0 ls5 ws6">3G/HD/SD-SDI Serializer with Comp<span class="ls6 ws7">lete SMPTE Audio <span class="ls7 ws8">& Video Support</span></span></div><div class="c x5 y7 w2 h4"><div class="t m0 x6 h5 y8 ff2 fs2 fc0 sc0 ls8 ws1">GS2972</div></div><div class="t m0 x7 h6 y9 ff3 fs3 fc1 sc0 ls9 ws1">www.semtech.com</div><div class="t m0 x3 h7 ya ff2 fs4 fc0 sc0 lsa ws9">Key Features</div><div class="t m0 x3 h6 yb ff3 fs3 fc0 sc0 lsb wsa">•<span class="_ _2"> </span>Operation at 2.970Gb/s, <span class="lsc wsb">2.970/1.001Gb/s, 1.485Gb/s, </span></div><div class="t m0 x8 h6 yc ff3 fs3 fc0 sc0 lsd wsc">1.485/1.001Gb/s and 270Mb/s</div><div class="t m0 x3 h6 yd ff3 fs3 fc0 sc0 lse wsd">•<span class="_ _2"> </span>Supports SMPTE ST 425 (Level<span class="_ _3"></span> A and Level B), <span class="ff4 ls1 ws1"> </span></div><div class="t m0 x8 h6 ye ff3 fs3 fc0 sc0 lsd wsc">SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and </div><div class="t m0 x8 h6 yf ff3 fs3 fc0 sc0 lsf ws1">DVB-ASI</div><div class="t m0 x3 h6 y10 ff3 fs3 fc0 sc0 ls10 wse">•<span class="_ _2"> </span>Integr<span class="_ _4"></span>ated Cable Driver</div><div class="t m0 x3 h6 y11 ff3 fs3 fc0 sc0 ls11 wsf">•<span class="_ _2"> </span>Integrated, low-noise VCO</div><div class="t m0 x3 h6 y12 ff3 fs3 fc0 sc0 ls12 ws10">•<span class="_ _2"> </span>Integr<span class="_ _4"></span>ated Narrow-Bandwi<span class="_ _4"></span>dth PLL</div><div class="t m0 x3 h6 y13 ff3 fs3 fc0 sc0 ls13 ws11">•<span class="_ _2"> </span>Integr<span class="_ _4"></span>ated Audio Embedder for up to 8 channels of </div><div class="t m0 x8 h6 y14 ff3 fs3 fc0 sc0 ls14 ws12">48kHz audio</div><div class="t m0 x3 h6 y15 ff3 fs3 fc0 sc0 ls15 ws13">•<span class="_ _2"> </span>Ancillary data insert<span class="_ _4"></span>ion</div><div class="t m0 x3 h6 y16 ff3 fs3 fc0 sc0 ls16 ws14">•<span class="_ _2"> </span>Optional conversion from SMPTE ST 425 Level A to </div><div class="t m0 x8 h6 y17 ff3 fs3 fc0 sc0 ls16 ws14">Level B for 1080p 50/60 4:2:2 10-bit</div><div class="t m0 x3 h6 y18 ff3 fs3 fc0 sc0 ls17 ws15">•<span class="_ _2"> </span>P<span class="_ _5"></span>arallel data bus selectable <span class="ls16 ws14">as either 20-bit or 10-bit</span></div><div class="t m0 x3 h6 y19 ff3 fs3 fc0 sc0 ls18 ws16">•<span class="_ _2"> </span>SMPTE video pr<span class="_ _4"></span>ocessing inc<span class="_ _4"></span>luding TRS calculation and </div><div class="t m0 x8 h6 y1a ff3 fs3 fc0 sc0 ls19 ws17">insertion, <span class="_ _3"></span>line number<span class="_ _3"></span> calculatio<span class="_ _3"></span>n and inse<span class="_ _3"></span>rtion, line<span class="_ _3"></span> </div><div class="t m0 x8 h6 y1b ff3 fs3 fc0 sc0 lsc wsb">based CRC calculation and <span class="ls1a ws18">insertion, illegal code </span></div><div class="t m0 x8 h6 y1c ff3 fs3 fc0 sc0 ls14 ws12">re-mapping, SMPTE ST 352 payload identifier </div><div class="t m0 x8 h6 y1d ff3 fs3 fc0 sc0 ls1b ws19">generation and in<span class="_ _3"></span>sertion</div><div class="t m0 x3 h6 y1e ff3 fs3 fc0 sc0 ls1c ws1a">•G<span class="_ _6"></span>S<span class="_ _6"></span>P<span class="_ _6"></span>I<span class="_ _6"></span> h<span class="_ _6"></span>o<span class="_ _6"></span>s<span class="_ _6"></span>t<span class="_ _6"></span> i<span class="_ _6"></span>n<span class="_ _6"></span>t<span class="_ _6"></span>e<span class="_ _6"></span>r<span class="_ _6"></span>f<span class="_ _7"></span>a<span class="_ _6"></span>c<span class="_ _6"></span>e</div><div class="t m0 x3 h6 y1f ff3 fs3 fc0 sc0 lsc wsb">•<span class="_ _2"> </span>+1.2V digital core power supply<span class="_ _5"></span>, +1.2V and +3.3V </div><div class="t m0 x8 h6 y20 ff3 fs3 fc0 sc0 ls1d ws1b">analog power supplies, a<span class="_ _4"></span>nd <span class="lsb wsa">selectable +1.8V or +3.3V </span></div><div class="t m0 x8 h6 y21 ff3 fs3 fc0 sc0 ls1e ws1c">I/O power supply</div><div class="t m0 x3 h6 y22 ff3 fs3 fc0 sc0 ls1f ws1d">•<span class="_ _0"> </span>-20ºC to +85ºC<span class="_ _4"></span> operati<span class="_ _4"></span>ng temper<span class="_ _4"></span>atur<span class="_ _4"></span>e ra<span class="_ _4"></span>nge</div><div class="t m0 x3 h6 y23 ff3 fs3 fc0 sc0 ls1d ws1e">•<span class="_ _2"> </span>Low power operation (typic<span class="_ _4"></span><span class="ls20 ws1f">ally at 400mW<span class="_ _5"></span>, including </span></div><div class="t m0 x8 h6 y24 ff3 fs3 fc0 sc0 ls21 ws20">Cable Driver)</div><div class="t m0 x3 h6 y25 ff3 fs3 fc0 sc0 lsb wsa">•<span class="_ _2"> </span>Small 11mm x 11mm 100-bal<span class="_ _3"></span>l BGA package</div><div class="t m0 x3 h6 y26 ff3 fs3 fc0 sc0 ls22 ws21">•<span class="_ _2"> </span>Pb-free and RoHS com<span class="_ _3"></span>pliant</div><div class="t m0 x9 h7 ya ff2 fs4 fc0 sc0 ls23 ws1">Applications</div><div class="c xa y27 w3 h8"><div class="t m1 x0 h9 y28 ff1 fs5 fc2 sc0 ls24 ws1">A<span class="_ _3"></span>p<span class="_ _8"></span>p<span class="_ _3"></span>lic<span class="_ _3"></span>a<span class="_ _3"></span>tio<span class="_ _8"></span>n:<span class="_ _3"></span><span class="ff5 ls1"> 1080p 50/60 Camera/Camcorder</span></div><div class="t m2 xb ha y29 ff5 fs6 fc2 sc0 ls25 ws1">ADC</div><div class="t m2 xc ha y2a ff5 fs6 fc2 sc0 ls26 ws1">Audio</div><div class="t m2 xd ha y2b ff5 fs6 fc2 sc0 ls27 ws1">Pr<span class="_ _3"></span>oc<span class="_ _3"></span>es<span class="_ _3"></span>s<span class="_ _3"></span>or</div><div class="t m2 xc ha y2c ff5 fs6 fc2 sc0 ls28 ws1">Vi<span class="_ _3"></span>deo</div><div class="t m2 xd ha y2d ff5 fs6 fc2 sc0 ls27 ws1">Pr<span class="_ _3"></span>oc<span class="_ _3"></span>es<span class="_ _3"></span>s<span class="_ _3"></span>or</div><div class="t m2 xe ha y2e ff5 fs6 fc2 sc0 ls25 ws1">CCD</div><div class="t m2 xf ha y2f ff5 fs6 fc2 sc0 ls29 ws1">20<span class="_ _8"> </span>-bi<span class="_ _3"></span>t</div><div class="t m2 x10 ha y30 ff5 fs6 fc2 sc0 ls2a ws1">GS29<span class="_ _4"></span>7<span class="_ _4"></span>2</div><div class="t m2 x11 ha y31 ff5 fs6 fc2 sc0 ls2b ws1">3G-<span class="_ _4"></span>S<span class="_ _4"></span>DI</div><div class="t m1 xf hb y32 ff5 fs7 fc2 sc0 ls1 ws1">HV<span class="_"> </span>F/PCLK</div><div class="t m1 x12 hb y33 ff5 fs7 fc2 sc0 ls1 ws1">CTRL/TIM<span class="_ _4"></span>E<span class="_ _3"> </span>C<span class="_ _3"></span>OD<span class="_ _3"></span>E</div><div class="t m2 x13 ha y34 ff5 fs6 fc2 sc0 ls1 ws1">AES - IN</div><div class="t m1 x14 hb y35 ff5 fs7 fc2 sc0 ls2c ws22">AUDI<span class="_ _4"></span>O 1<span class="_ _4"></span>/2</div><div class="t m1 x15 hb y36 ff5 fs7 fc2 sc0 ls2c ws23">AUDI<span class="_ _4"></span>O 3<span class="_ _4"></span>/<span class="_ _4"></span>4<span class="_ _9"></span><span class="ls2d ws24">Aud<span class="_ _4"></span>i<span class="_ _5"></span>o Cl<span class="_ _4"></span>o<span class="_ _4"></span>cks</span></div><div class="t m2 x16 ha y37 ff5 fs6 fc2 sc0 ls28 ws1">Stor<span class="_ _3"></span>age<span class="_ _3"></span>:</div><div class="t m2 x17 ha y38 ff5 fs6 fc2 sc0 ls29 ws25">T<span class="_ _3"></span>ape<span class="_ _8"> </span>/D<span class="_ _3"></span>i<span class="_ _8"> </span>s<span class="_ _3"></span>c<span class="_ _8"> </span>/<span class="_ _3"></span>Sol<span class="_ _3"></span>i<span class="_ _8"> </span>d Stat<span class="_ _3"></span>e</div><div class="t m2 x18 ha y39 ff5 fs6 fc2 sc0 ls2e ws1">MI<span class="_ _4"></span>C</div><div class="t m2 x19 ha y3a ff5 fs6 fc2 sc0 ls2f ws1">OPTIC<span class="_ _3"></span>S</div></div><div class="c x1a y3b w4 hc"><div class="t m3 x1b h9 y3c ff1 fs5 fc2 sc0 ls30 ws1">A<span class="_ _3"></span>p<span class="_ _8"></span>p<span class="_ _3"></span>lic<span class="_ _3"></span>a<span class="_ _3"></span>tio<span class="_ _3"></span>n<span class="_ _3"></span>:<span class="_ _3"></span><span class="ff5 ls1"> Dual Link (HD-SDI) </span></div><div class="t m3 x1b h9 y3d ff5 fs5 fc2 sc0 ls1 ws1">to Single Link (3G-SDI) Converter</div><div class="t m3 x1c ha y3e ff5 fs6 fc2 sc0 ls1 ws1">HD-SDI</div><div class="t m3 x1d ha y3f ff5 fs6 fc2 sc0 ls31 ws1">De<span class="_ _4"></span>se<span class="_ _4"></span>ria<span class="_ _4"></span>lize<span class="_ _5"></span>r</div><div class="t m3 x1d ha y40 ff5 fs6 fc2 sc0 ls1 ws1">(GS1559 or</div><div class="t m3 x1e ha y41 ff5 fs6 fc2 sc0 ls1 ws1">GS2970)</div><div class="t m3 x19 ha y42 ff5 fs6 fc2 sc0 ls32 ws26">Link<span class="_ _4"></span> A</div><div class="t m3 x1f ha y43 ff5 fs6 fc2 sc0 ls32 ws1">FIFO</div><div class="t m4 x20 hb y44 ff5 fs7 fc2 sc0 ls33 ws1">WR</div><div class="t m3 x1d ha y45 ff5 fs6 fc2 sc0 ls31 ws1">De<span class="_ _4"></span>se<span class="_ _4"></span>ria<span class="_ _4"></span>lize<span class="_ _5"></span>r</div><div class="t m3 x19 ha y46 ff5 fs6 fc2 sc0 ls32 ws26">Link<span class="_ _4"></span> B</div><div class="t m3 x1f ha y47 ff5 fs6 fc2 sc0 ls32 ws1">FIFO</div><div class="t m4 x20 hb y48 ff5 fs7 fc2 sc0 ls33 ws1">WR</div><div class="t m3 x21 ha y49 ff5 fs6 fc2 sc0 ls2a ws1">GS2972</div><div class="t m3 x22 ha y4a ff5 fs6 fc2 sc0 ls1 ws1">GS4910</div><div class="t m3 x23 ha y4b ff5 fs6 fc2 sc0 ls1 ws1">10-bit</div><div class="t m3 x24 ha y4c ff5 fs6 fc2 sc0 ls2a ws1">3G-SDI</div><div class="t m4 x25 hb y4d ff5 fs7 fc2 sc0 ls34 ws1">HVF</div><div class="t m4 x20 hb y4e ff5 fs7 fc2 sc0 ls35 ws1">XT<span class="_ _4"></span>AL</div><div class="t m4 x26 hb y4f ff5 fs7 fc2 sc0 ls1 ws1">HV<span class="_"> </span>F/PCLK</div><div class="t m4 x26 hb y50 ff5 fs7 fc2 sc0 ls1 ws1">HV<span class="_"> </span>F/PCLK</div><div class="t m4 x27 hb y51 ff5 fs7 fc2 sc0 ls1 ws1">HV<span class="_"> </span>F/PCLK</div><div class="t m3 x1d ha y52 ff5 fs6 fc2 sc0 ls1 ws1">(GS1559 or</div><div class="t m3 x1e ha y53 ff5 fs6 fc2 sc0 ls1 ws1">GS2970)</div><div class="t m3 x23 ha y54 ff5 fs6 fc2 sc0 ls1 ws1">10-bit</div><div class="t m3 x28 ha y55 ff5 fs6 fc2 sc0 ls1 ws1">10-bit</div><div class="t m3 x25 ha y56 ff5 fs6 fc2 sc0 ls1 ws1">10-bit</div><div class="t m3 x1c ha y57 ff5 fs6 fc2 sc0 ls1 ws1">HD-SDI</div><div class="t m3 x0 ha y58 ff5 fs6 fc2 sc0 ls1 ws1">HD-SDI</div><div class="t m3 x0 ha y59 ff5 fs6 fc2 sc0 ls1 ws1">HD-SDI</div><div class="t m3 x29 ha y5a ff5 fs6 fc2 sc0 ls1 ws1">EQ</div><div class="t m3 x29 ha y5b ff5 fs6 fc2 sc0 ls1 ws1">EQ</div><div class="t m5 x2a hd y5c ff5 fs8 fc2 sc0 ls1 ws1">GS2974B</div><div class="t m5 x2a hd y5d ff5 fs8 fc2 sc0 ls1 ws1">GS2974B</div></div><div class="c x2b y5e w5 he"><div class="t m1 x18 h9 y5f ff1 fs5 fc2 sc0 ls24 ws1">A<span class="_ _3"></span>p<span class="_ _8"></span>p<span class="_ _3"></span>lic<span class="_ _3"></span>a<span class="_ _3"></span>tio<span class="_ _8"></span>n:<span class="_ _3"></span><span class="ff5 ls1"> Multi-format Audio Embedder Module</span></div><div class="t m2 x0 ha y60 ff5 fs6 fc2 sc0 ls1 ws1">SD/HD/3G-SDI</div><div class="t m1 x2c hb y61 ff5 fs7 fc2 sc0 ls36 ws1">PCL<span class="_ _5"></span>K</div><div class="t m2 x2d ha y62 ff5 fs6 fc2 sc0 ls37 ws1">10<span class="_ _8"> </span>-<span class="_ _3"></span>b<span class="_ _3"></span>i<span class="_ _3"></span>t</div><div class="t m2 x25 ha y60 ff5 fs6 fc2 sc0 ls1 ws1">GS2970</div><div class="t m2 x2e ha y63 ff5 fs6 fc2 sc0 ls2a ws1">GS2972</div><div class="t m2 x2f ha y64 ff5 fs6 fc2 sc0 ls25 ws1">ADC</div><div class="t m2 xf ha y65 ff5 fs6 fc2 sc0 ls25 ws1">S<span class="_ _4"></span>witc<span class="_ _4"></span>h<span class="_ _4"></span> </div><div class="t m2 x30 ha y66 ff5 fs6 fc2 sc0 ls29 ws1">Logi<span class="_ _3"></span>c</div><div class="t m2 x12 ha y67 ff5 fs6 fc2 sc0 ls1 ws1">&</div><div class="t m2 xf ha y68 ff5 fs6 fc2 sc0 ls28 ws1">Buffer<span class="_ _3"></span>s</div><div class="t m2 x31 ha y69 ff5 fs6 fc2 sc0 ls1 ws1">SD/HD/3G-SDI</div><div class="t m2 x18 ha y64 ff5 fs6 fc2 sc0 ls31 ws1">Ana<span class="_ _4"></span>l<span class="_ _4"></span>og</div><div class="t m2 x32 ha y6a ff5 fs6 fc2 sc0 ls32 ws1">Audio</div><div class="t m2 x32 ha y6b ff5 fs6 fc2 sc0 ls2f ws1">Inp<span class="_ _3"></span>u<span class="_ _3"></span>t<span class="_ _3"></span>s</div><div class="t m2 x33 ha y6c ff5 fs6 fc2 sc0 ls31 ws1">AE<span class="_ _4"></span>S</div><div class="t m2 x32 ha y6d ff5 fs6 fc2 sc0 ls32 ws1">Audio</div><div class="t m2 x32 ha y6e ff5 fs6 fc2 sc0 ls2f ws1">Inp<span class="_ _3"></span>u<span class="_ _3"></span>t<span class="_ _3"></span>s</div><div class="t m1 x2d hb y6f ff5 fs7 fc2 sc0 ls34 ws27">AUDI<span class="_ _4"></span>O 1<span class="_ _4"></span>/2</div><div class="t m1 x2d hb y70 ff5 fs7 fc2 sc0 ls34 ws27">AUDI<span class="_ _4"></span>O 3<span class="_ _4"></span>/4</div><div class="t m1 x2d hb y71 ff5 fs7 fc2 sc0 ls34 ws27">AUDI<span class="_ _4"></span>O 5<span class="_ _4"></span>/6</div><div class="t m1 x2d hb y72 ff5 fs7 fc2 sc0 ls34 ws27">AUDI<span class="_ _4"></span>O 7<span class="_ _4"></span>/8</div><div class="t m2 x34 ha y73 ff5 fs6 fc2 sc0 ls28 ws1">SR<span class="_ _3"></span>C</div><div class="t m2 x35 ha y74 ff5 fs6 fc2 sc0 ls1 ws1">GS4911</div><div class="t m6 x36 hf y75 ff5 fs9 fc2 sc0 ls38 ws1">XTA<span class="_ _4"></span>L</div><div class="t m1 x12 hb y76 ff5 fs7 fc2 sc0 ls34 ws1">HVF</div><div class="t m1 x37 hb y77 ff5 fs7 fc2 sc0 ls39 ws28">Audio C<span class="_ _3"></span>locks</div><div class="t m2 x3 ha y78 ff5 fs6 fc2 sc0 ls1 ws1">EQ</div><div class="t m5 x37 hd y79 ff5 fs8 fc2 sc0 ls3a ws1">GS2974B</div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/638f674197bc301588149cdc/bg2.jpg"><div class="t m0 x38 h2 y1 ff1 fs0 fc0 sc0 ls0 ws29">2 of 125</div><div class="t m0 x39 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1"> </div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls2 ws2">GS2972 3G/HD/SD-SDI Serializer with Complete </div><div class="t m0 x3 h2 y3 ff1 fs0 fc0 sc0 ls3 ws3">SMPTE Audio & Video Support</div><div class="t m0 x3 h2 y4 ff1 fs0 fc0 sc0 ls1 ws4">Final Data Sheet<span class="_ _0"> </span>Rev. 9</div><div class="t m0 x3 h2 y5 ff1 fs0 fc0 sc0 ls4 ws5">GENDOC-047479<span class="_ _1"> </span>September 2013</div><div class="t m0 x7 h6 y9 ff3 fs3 fc1 sc0 ls20 ws1">www.semtech.com</div><div class="t m0 x3a h7 y7a ff2 fs4 fc0 sc0 ls3b ws1">Description</div><div class="t m0 x3a h6 y7b ff3 fs3 fc0 sc0 ls3c ws2a">The GS2972 is a complete SDI <span class="ls3d ws1">Transmitter, <span class="ls3e ws2b">generating a </span></span></div><div class="t m0 x3a h6 y7c ff3 fs3 fc0 sc0 lsc ws2c">SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C or DVB-ASI </div><div class="t m0 x3a h6 y7d ff3 fs3 fc0 sc0 ls3f ws2d">compliant <span class="_ _3"></span>serial digital o<span class="_ _3"></span>utput signal<span class="_ _3"></span>.</div><div class="t m0 x3a h6 y7e ff3 fs3 fc0 sc0 ls40 ws2e">The integrated<span class="_ _3"></span> Narrow BW PLL allows <span class="_ _3"></span>the device to<span class="_ _3"></span> accept </div><div class="t m0 x3a h6 y7f ff3 fs3 fc0 sc0 ls22 ws21">parallel cloc<span class="_ _3"></span>ks with high inpu<span class="_ _3"></span>t jitter, and <span class="_ _3"></span>still provide<span class="_ _3"></span> a </div><div class="t m0 x3a h6 y80 ff3 fs3 fc0 sc0 ls41 ws1">SMPTE compliant <span class="_ _3"></span>serial digital o<span class="_ _3"></span>utput.</div><div class="t m0 x3a h6 y81 ff3 fs3 fc0 sc0 ls42 ws2f">The device can operat<span class="_ _3"></span>e in four basic user selectable modes: </div><div class="t m0 x3a h6 y82 ff3 fs3 fc0 sc0 ls3d ws30">SMPTE mode, DVB-ASI mod<span class="_ _3"></span>e, Data-Through mode, or<span class="_ _3"></span> </div><div class="t m0 x3a h6 y83 ff3 fs3 fc0 sc0 ls43 ws31">Standby mo<span class="_ _4"></span>de.</div><div class="t m0 x3a h6 y84 ff3 fs3 fc0 sc0 lsd ws32">In SMPTE mode, the GS2972 perf<span class="ls44 ws33">orms all SMPTE processing </span></div><div class="t m0 x3a h6 y85 ff3 fs3 fc0 sc0 ls45 ws34">features. Both SMPTE ST 42<span class="_ _3"></span>5 Level A and Level B formats </div><div class="t m0 x3a h6 y86 ff3 fs3 fc0 sc0 ls46 ws35">are supporte<span class="_ _4"></span>d with optional conver<span class="_ _4"></span>sion from Level A to </div><div class="t m0 x3a h6 y87 ff3 fs3 fc0 sc0 ls16 ws14">Level B for 1080p 50/60 4:2:2 10-bit.</div><div class="t m0 x3a h6 y88 ff3 fs3 fc0 sc0 ls17 ws36">In DVB-ASI mode, the de<span class="_ _3"></span>vice will perform 8b/10b encod<span class="_ _3"></span>ing </div><div class="t m0 x3a h6 y89 ff3 fs3 fc0 sc0 ls47 ws37">prior to transmission.</div><div class="t m0 x3a h6 y8a ff3 fs3 fc0 sc0 ls48 ws38">In Data-Through mode, all SMPTE and<span class="_ _3"></span> DVB-ASI processing </div><div class="t m0 x3a h6 y8b ff3 fs3 fc0 sc0 ls41 ws1">is disabled. The<span class="_ _3"></span> device can be used<span class="_ _3"></span> as a simple par<span class="_ _3"></span>allel to </div><div class="t m0 x3a h6 y8c ff3 fs3 fc0 sc0 ls49 ws39">serial conv<span class="_ _3"></span>erter.</div><div class="t m0 x3a h6 y8d ff3 fs3 fc0 sc0 ls49 ws3a">The device ca<span class="_ _3"></span>n also oper<span class="_ _3"></span>ate in a l<span class="_ _3"></span>ower power St<span class="_ _3"></span>andby </div><div class="t m0 x3a h6 y8e ff3 fs3 fc0 sc0 lsb wsa">mode. In this mode, no signal<span class="ls3f ws2d"> i<span class="_ _3"></span>s generated at<span class="_ _3"></span> the output.</span></div><div class="t m0 x3a h6 y8f ff3 fs3 fc0 sc0 lsb wsa">The GS2972 integrates a fully SMPTE-compliant <span class="_ _3"></span>Cable </div><div class="t m0 x3a h6 y90 ff3 fs3 fc0 sc0 lsb wsa">Driver for SMPTE ST 259-C, SMPTE ST 292 and <span class="_ _3"></span><span class="ff4 ls1 ws1"> </span></div><div class="t m0 x3a h6 y91 ff3 fs3 fc0 sc0 ls14 ws12">SMPTE ST 424 interfaces. It <span class="ls16 ws14">features automatic dual </span></div><div class="t m0 x3a h6 y92 ff3 fs3 fc0 sc0 ls4a ws3b">slew-rate selection, depe<span class="_ _4"></span>nding on 3Gb/s or HD or SD </div><div class="t m0 x3a h6 y93 ff3 fs3 fc0 sc0 ls4b ws3c">operationa<span class="_ _4"></span>l requirements.</div><div class="t m0 x3a h6 y94 ff3 fs3 fc0 sc0 lsb ws3d">In accordance with SMPTE ST 272 and SMPTE <span class="_ _3"></span>ST 299, up to </div><div class="t m0 x3a h6 y95 ff3 fs3 fc0 sc0 ls1a ws18">eight channels (two <span class="ls1 ws3e">audio groups) of serial digital aud<span class="_ _3"></span>io </span></div><div class="t m0 x3a h6 y96 ff3 fs3 fc0 sc0 ls4c ws3f">may be embedd<span class="_ _3"></span>ed into th<span class="_ _3"></span>e video data stre<span class="_ _3"></span>am.The input </div><div class="t m0 x3a h6 y97 ff3 fs3 fc0 sc0 lsf ws40">audio signal formats supported by the device include </div><div class="t m0 x3a h6 y98 ff3 fs3 fc0 sc0 ls13 ws11">AES/EBU, I</div><div class="t m0 x3b h10 y99 ff3 fs0 fc0 sc0 ls1 ws1">2</div><div class="t m0 x3c h6 y9a ff3 fs3 fc0 sc0 ls16 ws14">S and serial audio. 16, 20 and 24-bit audio </div><div class="t m0 x3a h6 y9b ff3 fs3 fc0 sc0 ls15 ws41">formats are supported at 48kHz<span class="ws42"> synchronous<span class="_ _4"></span> for SD modes </span></div><div class="t m0 x3a h6 y9c ff3 fs3 fc0 sc0 ls16 ws14">and 48kHz synchronous or asynchro<span class="_ _3"></span>nous in HD, 3Gb/s </div><div class="t m0 x3a h6 y9d ff3 fs3 fc0 sc0 ls43 ws1">modes.</div><div class="c xd y9e w6 h11"><div class="t m1 x3d h9 y9f ff1 fs5 fc2 sc0 ls24 ws1">A<span class="_ _3"></span>p<span class="_ _8"></span>p<span class="_ _3"></span>lic<span class="_ _3"></span>a<span class="_ _3"></span>tio<span class="_ _8"></span>n:<span class="_ _3"></span> <span class="_ _3"></span><span class="ff5 ls1">Multi-format Digital VTR/Video Server</span></div><div class="t m3 x3e ha ya0 ff5 fs6 fc2 sc0 ls27 ws1">Stor<span class="_ _8"> </span>age<span class="_ _8"> </span>:</div><div class="t m3 x19 ha ya1 ff5 fs6 fc2 sc0 ls27 ws25">T<span class="_ _3"></span>ape<span class="_ _8"> </span>/<span class="_ _8"> </span>H<span class="_ _3"></span>D<span class="_ _8"> </span>D/Sol<span class="_ _3"></span>i<span class="_ _3"></span>d S<span class="_ _3"></span>tat<span class="_ _3"></span>e</div><div class="t m3 x26 ha ya2 ff5 fs6 fc2 sc0 ls26 ws1">Audio</div><div class="t m3 x3f ha ya3 ff5 fs6 fc2 sc0 ls26 ws1">Pr<span class="_ _3"></span>oces<span class="_ _3"></span>sor</div><div class="t m3 x26 ha ya4 ff5 fs6 fc2 sc0 ls26 ws1">Vi<span class="_ _3"></span>deo</div><div class="t m3 x3f ha ya5 ff5 fs6 fc2 sc0 ls26 ws1">Pr<span class="_ _3"></span>oces<span class="_ _3"></span>sor</div><div class="t m3 x40 ha ya6 ff5 fs6 fc2 sc0 ls29 ws1">20<span class="_ _8"> </span>-bi<span class="_ _3"></span>t</div><div class="t m1 x2c hb ya7 ff5 fs7 fc2 sc0 ls34 ws1">HVF/PCL<span class="_ _4"></span>K</div><div class="t m1 x41 hb ya8 ff5 fs7 fc2 sc0 ls4d ws43">Audio Inputs</div><div class="t m8 x42 h12 ya9 ff5 fsa fc2 sc0 ls4e ws44">V<span class="_"> </span>i<span class="_ _4"></span>deo Inputs</div><div class="t m3 x40 ha yaa ff5 fs6 fc2 sc0 ls2a ws1">GS4911</div><div class="t m1 x43 hb yab ff5 fs7 fc2 sc0 ls39 ws28">Audio C<span class="_ _3"></span>locks</div><div class="t m3 x44 ha yac ff5 fs6 fc2 sc0 ls2a ws1">GS2972</div><div class="t m3 x24 ha yad ff5 fs6 fc2 sc0 ls1 ws1">3G-SDI</div><div class="t m3 x45 ha yae ff5 fs6 fc2 sc0 ls28 ws1">Sync</div><div class="t m3 x46 ha yaf ff5 fs6 fc2 sc0 ls28 ws1">Seperator</div><div class="t m3 x47 ha yb0 ff5 fs6 fc2 sc0 ls4f ws1">Ana<span class="_ _4"></span>l<span class="_ _4"></span>og</div><div class="t m3 x47 ha yb1 ff5 fs6 fc2 sc0 ls28 ws1">Sync</div><div class="t m1 x2c hb yb2 ff5 fs7 fc2 sc0 ls2c ws45">AUDI<span class="_ _4"></span>O 1<span class="_ _4"></span>/2</div><div class="t m1 x2c hb yb3 ff5 fs7 fc2 sc0 ls2c ws45">AUDI<span class="_ _4"></span>O 3<span class="_ _4"></span>/4</div><div class="t m1 x2c hb yb4 ff5 fs7 fc2 sc0 ls2c ws45">AUDI<span class="_ _4"></span>O 5<span class="_ _4"></span>/6</div><div class="t m1 x2c hb yb5 ff5 fs7 fc2 sc0 ls2c ws45">AUDI<span class="_ _4"></span>O 7<span class="_ _4"></span>/8</div><div class="t m1 x48 hb yb6 ff5 fs7 fc2 sc0 ls35 ws1">XT<span class="_ _4"></span>AL</div></div><div class="c x3 yb7 w7 h13"><div class="t m2 x49 ha yb8 ff5 fs6 fc2 sc0 ls26 ws1"><span class="fc3 sc0">Ke</span><span class="fc3 sc0">y</span><span class="fc3 sc0">e</span><span class="fc3 sc0">r</span></div><div class="t m2 x14 ha yb9 ff5 fs6 fc2 sc0 ls26 ws1"><span class="fc3 sc0">Ke</span><span class="fc3 sc0">y</span><span class="fc3 sc0">e</span><span class="fc3 sc0">r</span></div><div class="t m1 x4a h9 yba ff1 fs5 fc2 sc0 ls24 ws1">A<span class="_ _3"></span>p<span class="_ _8"></span>p<span class="_ _3"></span>lic<span class="_ _3"></span>a<span class="_ _3"></span>tio<span class="_ _8"></span>n:<span class="_ _3"></span> <span class="_ _3"></span><span class="ff5 ls1">Multi-format Presentation Switcher</span></div><div class="t m1 x14 h9 ybb ff5 fs5 fc2 sc0 ls1 ws1">(Output Stage)<span class="ff1"> </span></div><div class="t m2 x18 ha ybc ff5 fs6 fc2 sc0 ls31 ws1">DV<span class="_ _4"></span>E<span class="_ _a"> </span><span class="ls2e">Mixe<span class="_ _5"></span>rs<span class="_ _b"> </span><span class="ls31 ws46">K<span class="_ _4"></span>e<span class="_ _4"></span>y &<span class="_ _4"></span> F<span class="_ _4"></span>ill</span></span></div><div class="t m2 x4b ha ybd ff5 fs6 fc2 sc0 ls27 ws1">Logo </div><div class="t m2 x4c ha ybe ff5 fs6 fc2 sc0 ls50 ws1">Inserter</div><div class="t m2 x23 ha ybf ff5 fs6 fc2 sc0 ls37 ws1">Im<span class="_ _8"> </span>age </div><div class="t m2 x23 ha yc0 ff5 fs6 fc2 sc0 ls26 ws1">Stor<span class="_ _3"></span>e</div><div class="t m2 x1b ha yc1 ff5 fs6 fc2 sc0 ls2f ws1">Key<span class="_ _3"></span>/F<span class="_ _3"></span>ill </div><div class="t m2 x2f ha yc2 ff5 fs6 fc2 sc0 ls2f ws1">Inp<span class="_ _3"></span>u<span class="_ _3"></span>t<span class="_ _3"></span>s</div><div class="t m2 x4d ha yc3 ff5 fs6 fc2 sc0 ls2a ws1">GS2972<span class="_ _c"></span><span class="ls37 ws47">10<span class="_ _8"> </span>-<span class="_ _3"></span>b<span class="_ _3"></span>i<span class="_ _3"></span>t<span class="_ _3"></span> +<span class="_"> </span> C<span class="_ _3"></span>lk</span></div><div class="t m2 x4e ha yc4 ff5 fs6 fc2 sc0 ls37 ws47">20<span class="_ _8"> </span>-<span class="_ _3"></span>b<span class="_ _3"></span>i<span class="_ _3"></span>t<span class="_ _3"></span> +<span class="_"> </span> C<span class="_ _3"></span>lk</div><div class="t m2 x47 ha yc5 ff5 fs6 fc2 sc0 ls1 ws1">SD/HD/3G-SDI</div><div class="t m2 x4f ha yc6 ff5 fs6 fc2 sc0 ls2f ws1">Au<span class="_ _3"></span>xiliary</div><div class="t m2 x4f ha yc7 ff5 fs6 fc2 sc0 ls26 ws1">Preview</div><div class="t m2 x50 ha yc8 ff5 fs6 fc2 sc0 ls26 ws1">Pro<span class="_ _3"></span>g<span class="_ _3"></span>ram</div><div class="t m2 x51 ha yc9 ff5 fs6 fc2 sc0 ls26 ws1">Audio</div><div class="t m2 x51 ha yca ff5 fs6 fc2 sc0 ls51 ws1">Mixe<span class="_ _5"></span>r</div><div class="t m1 x3f hb ycb ff5 fs7 fc2 sc0 ls4d ws48">AE<span class="_"> </span>S<span class="_"> </span> from<span class="_"> </span> Input De<span class="_"> </span>mux</div><div class="t m1 x52 hb ycc ff5 fs7 fc2 sc0 ls1 ws1">V<span class="_ _3"> </span>oice-Over</div><div class="t m1 x53 hb ycd ff5 fs7 fc2 sc0 ls52 ws1">P<span class="_"> </span>r<span class="_ _3"></span>e<span class="_"> </span>se<span class="_"> </span>t<span class="_ _3"></span> A<span class="_"> </span>E<span class="_"> </span>S<span class="_"> </span> In</div><div class="t m1 x35 hb yce ff5 fs7 fc2 sc0 ls53 ws49">Pr<span class="_ _4"></span>o<span class="_ _4"></span>g<span class="_ _4"></span>r<span class="_ _4"></span>am<span class="_ _4"></span> AES I<span class="_ _5"></span>n</div><div class="t m1 x54 hb ycf ff5 fs7 fc2 sc0 ls54 ws48">P<span class="_"> </span>rogram<span class="_"> </span> AE<span class="_"> </span>S<span class="_"> </span> Out</div><div class="t m1 x54 hb yd0 ff5 fs7 fc2 sc0 ls52 ws4a">P<span class="_"> </span>r<span class="_ _3"></span>e<span class="_"> </span>vie<span class="_"> </span>w A<span class="_"> </span>E<span class="_"> </span>S<span class="_"> </span> O<span class="_"> </span>ut</div><div class="t m1 x55 hb yd1 ff5 fs7 fc2 sc0 ls55 ws4b">I2S<span class="_"> </span> Audio <span class="_ _d"> </span>+ <span class="_"> </span>C<span class="_ _3"></span>locks</div><div class="t m2 x4e ha yb9 ff5 fs6 fc2 sc0 ls37 ws47">20<span class="_ _8"> </span>-<span class="_ _3"></span>b<span class="_ _3"></span>i<span class="_ _3"></span>t<span class="_ _3"></span> +<span class="_"> </span> C<span class="_ _3"></span>lk</div><div class="t m2 x43 ha yd2 ff5 fs6 fc2 sc0 ls1 ws1">GS4911</div><div class="t m2 x56 ha yd3 ff5 fs6 fc2 sc0 ls31 ws1">Ana<span class="_ _4"></span>l<span class="_ _4"></span>og</div><div class="t m2 x57 ha yd4 ff5 fs6 fc2 sc0 ls28 ws1">Sync</div><div class="t m1 x40 hb yd5 ff5 fs7 fc2 sc0 ls56 ws1">XT<span class="_ _4"></span>AL</div><div class="t m2 x58 ha yd6 ff5 fs6 fc2 sc0 ls28 ws1">Sync</div><div class="t m2 x59 ha yd7 ff5 fs6 fc2 sc0 ls28 ws1">Seperator</div><div class="t m2 x46 ha yd6 ff5 fs6 fc2 sc0 ls31 ws4c">Clo<span class="_ _4"></span>c<span class="_ _4"></span>k<span class="_ _4"></span> &</div><div class="t m2 x46 ha yd7 ff5 fs6 fc2 sc0 ls32 ws4d">Sy<span class="_ _5"></span>nc Dis<span class="_ _5"></span>t<span class="_ _3"></span>ributi<span class="_ _4"></span>on</div><div class="t m2 x4d ha yd8 ff5 fs6 fc2 sc0 ls2a ws1">GS2972</div><div class="t m2 x4d ha yd9 ff5 fs6 fc2 sc0 ls2a ws1">GS2972</div><div class="t m2 x5a ha yda ff5 fs6 fc2 sc0 ls1 ws1">SD/HD/3G-SDI</div><div class="t m2 x5a ha ydb ff5 fs6 fc2 sc0 ls1 ws1">SD/HD/3G-SDI</div></div><div class="c x16 ydc w8 h14"><div class="t m9 x5b h15 ydd ff1 fsb fc2 sc0 ls57 ws1">A<span class="_ _3"></span>p<span class="_ _8"></span>p<span class="_ _3"></span>lic<span class="_ _3"></span>a<span class="_ _3"></span>tio<span class="_ _8"></span>n:<span class="_ _3"></span><span class="ff5 ls1"> 3Gb/s SDI Test Signal Generator</span></div><div class="t m9 x59 h16 yde ff5 fsc fc2 sc0 ls1 ws1">GS4911</div><div class="t m9 x0 h16 ydf ff5 fsc fc2 sc0 ls58 ws1">Ana<span class="_ _4"></span>l<span class="_ _4"></span>og</div><div class="t m9 x5c h16 ye0 ff5 fsc fc2 sc0 ls59 ws1">Sync</div><div class="t m9 xb h16 ye1 ff5 fsc fc2 sc0 ls59 ws1">Sync</div><div class="t m9 x4a h16 ye2 ff5 fsc fc2 sc0 ls59 ws1">Seperator</div><div class="t m9 x10 h16 ye3 ff5 fsc fc2 sc0 ls59 ws1">Vi<span class="_ _3"></span>deo </div><div class="t m9 x10 h16 ye4 ff5 fsc fc2 sc0 ls59 ws1">Si<span class="_ _3"></span>gnal</div><div class="t m9 x5d h16 ye5 ff5 fsc fc2 sc0 ls5a ws1">Gen<span class="_ _4"></span>er<span class="_ _3"></span>ato<span class="_ _4"></span>r<span class="_ _3"></span> </div><div class="t m1 x58 hb ye6 ff5 fs7 fc2 sc0 ls35 ws1">XT<span class="_ _4"></span>AL</div><div class="t ma x10 h16 ye7 ff5 fsc fc2 sc0 ls5b ws1">Audio</div><div class="t ma x5d h16 ye8 ff5 fsc fc2 sc0 ls5a ws1">Gen<span class="_ _4"></span>er<span class="_ _3"></span>ato<span class="_ _4"></span>r<span class="_ _3"></span> </div><div class="t ma x48 h16 ye9 ff5 fsc fc2 sc0 ls5c ws1">Me<span class="_ _4"></span>mo<span class="_ _4"></span>ry</div><div class="t m1 x30 hb yea ff5 fs7 fc2 sc0 ls1 ws1">HV<span class="_"> </span>F/PCLK</div><div class="t m1 x25 hb yeb ff5 fs7 fc2 sc0 ls5d ws4b">Audio C<span class="_ _3"></span>locks</div><div class="t ma x5e h16 yec ff5 fsc fc2 sc0 ls5e ws1">20<span class="_ _8"> </span>-<span class="_ _3"></span>b<span class="_ _3"></span>i<span class="_ _3"></span>t</div><div class="t ma x5f h16 yed ff5 fsc fc2 sc0 ls2a ws1">GS2972</div><div class="t ma x24 h16 yee ff5 fsc fc2 sc0 ls1 ws1">3G-SDI</div><div class="t m1 x5e hb yef ff5 fs7 fc2 sc0 ls5f ws4e">AES<span class="_ _3"></span> 1/2</div><div class="t m1 x5e hb yf0 ff5 fs7 fc2 sc0 ls5f ws4e">AES<span class="_ _3"></span> 3/4</div><div class="t m1 x5e hb yf1 ff5 fs7 fc2 sc0 ls5f ws4e">AES<span class="_ _3"></span> 5/6</div><div class="t m1 x5e hb yf2 ff5 fs7 fc2 sc0 ls5f ws4e">AES<span class="_ _3"></span> 7/8</div><div class="t m1 x5e hb yf3 ff5 fs7 fc2 sc0 ls1 ws1">HV<span class="_"> </span>F/PCLK</div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/638f674197bc301588149cdc/bg3.jpg"><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls2 ws2">GS2972 3G/HD/SD-SDI Serializer with Complete </div><div class="t m0 x3 h2 y3 ff1 fs0 fc0 sc0 ls3 ws3">SMPTE Audio & Video Support</div><div class="t m0 x3 h2 y4 ff1 fs0 fc0 sc0 ls1 ws4">Final Data Sheet<span class="_ _0"> </span>Rev. 9</div><div class="t m0 x3 h2 y5 ff1 fs0 fc0 sc0 ls4 ws5">GENDOC-047479<span class="_ _1"> </span>September 2013</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">3 of 125</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h6 y9 ff3 fs3 fc1 sc0 ls9 ws1">www.semtech.com</div><div class="t m0 x3 h7 y7a ff2 fs4 fc0 sc0 ls60 ws4f">Functional Block Diagram</div><div class="t m0 x60 h17 yf4 ff1 fsd fc0 sc0 ls61 ws50">Figure A: GS2972 Fun<span class="ff6 ls1 ws1">c</span><span class="ls60 ws51">tional Blo<span class="ff6 ls1 ws1">c</span><span class="ls62 ws52">k Dia<span class="_ _3"></span>gram</span></span></div><div class="t mb x20 h18 yf5 ff5 fse fc4 sc0 ls63 ws1">Input</div><div class="t mb x61 h18 yf6 ff5 fse fc4 sc0 ls1 ws1">Mux/</div><div class="t mb x62 h18 yf7 ff5 fse fc4 sc0 ls1 ws1">Demux</div><div class="t mc x59 h19 yf8 ff5 fsf fc4 sc0 ls64 ws1">DIN[19:0]</div><div class="t mb x63 h18 yf9 ff5 fse fc4 sc0 ls1 ws53">ANC D<span class="_ _3"></span>ata</div><div class="t mb x63 h18 yfa ff5 fse fc4 sc0 ls1 ws1">Insertion </div><div class="t mb x2b h18 yfb ff5 fse fc4 sc0 ls65 ws54">TRS<span class="_ _e"> </span>, Li<span class="_ _3"></span>n<span class="_ _3"></span>e<span class="_ _3"></span> </div><div class="t mb x1a h18 yfc ff5 fse fc4 sc0 ls63 ws1">Number </div><div class="t mb x2b h18 yfd ff5 fse fc4 sc0 ls63 ws55">and CRC </div><div class="t mb x2b h18 yfe ff5 fse fc4 sc0 ls1 ws1">Insertion</div><div class="t mb x64 h18 yff ff5 fse fc4 sc0 ls66 ws1">EDH</div><div class="t mb x65 h18 y100 ff5 fse fc4 sc0 ls66 ws1">Packet</div><div class="t mb x66 h18 y101 ff5 fse fc4 sc0 ls1 ws1">Insertion </div><div class="t mb x67 h18 y102 ff5 fse fc4 sc0 ls1 ws1">DVB-ASI</div><div class="t mb x68 h18 y103 ff5 fse fc4 sc0 ls66 ws1">8b/10b</div><div class="t mb x67 h18 y104 ff5 fse fc4 sc0 ls1 ws1">Encoder</div><div class="t mc x8 h19 y105 ff5 fsf fc4 sc0 ls1 ws1">F/DE</div><div class="t mc x69 h19 y106 ff5 fsf fc4 sc0 ls1 ws1">V/VSYNC</div><div class="t mc x69 h19 y107 ff5 fsf fc4 sc0 ls1 ws1">H/HSYNC</div><div class="t mc xc h19 y108 ff5 fsf fc4 sc0 ls1 ws1">TIM_861</div><div class="t mb x6a h18 yf9 ff5 fse fc4 sc0 ls1 ws53">Paral<span class="_ _3"></span>le<span class="_ _3"></span>l to Seri<span class="_ _3"></span>al</div><div class="t mb x6b h18 yfa ff5 fse fc4 sc0 ls1 ws1">Converter </div><div class="t mb x6c h18 y109 ff5 fse fc4 sc0 ls66 ws1">Mux</div><div class="t mb x6d h18 yff ff5 fse fc4 sc0 ls1 ws1">SMPTE</div><div class="t mb x6e h18 y100 ff5 fse fc4 sc0 ls1 ws1">Cable</div><div class="t mb x6d h18 y101 ff5 fse fc4 sc0 ls1 ws1">Driver</div><div class="t mc x6f h19 y10a ff5 fsf fc4 sc0 ls67 ws1">SDO</div><div class="t mc x6f h19 y10b ff5 fsf fc4 sc0 ls67 ws1">SDO</div><div class="t mc x6f h19 y10c ff5 fsf fc4 sc0 ls68 ws1">RSE<span class="_ _4"></span>T</div><div class="t mc x6f h19 y10d ff5 fsf fc4 sc0 ls69 ws1">SDO_EN/DIS</div><div class="t mc x70 h19 y10e ff5 fsf fc4 sc0 ls6a ws1">PCLK</div><div class="t mc x71 h19 y10f ff5 fsf fc4 sc0 ls6a ws1">ACLK<span class="_ _3"></span>1</div><div class="t mc x71 h19 y110 ff5 fsf fc4 sc0 ls6a ws1">ACLK<span class="_ _3"></span>2</div><div class="t mc x72 h19 y111 ff5 fsf fc4 sc0 ls6b ws1">WCLK<span class="_ _3"></span>1</div><div class="t mc x72 h19 y112 ff5 fsf fc4 sc0 ls6b ws1">WCLK<span class="_ _3"></span>2</div><div class="t mc x72 h19 y113 ff5 fsf fc4 sc0 ls69 ws1">Ai<span class="_ _4"></span>n_1/2</div><div class="t mc x72 h19 y114 ff5 fsf fc4 sc0 ls69 ws1">Ai<span class="_ _4"></span>n_3/4</div><div class="t mc x72 h19 y115 ff5 fsf fc4 sc0 ls69 ws1">Ai<span class="_ _4"></span>n_5/6</div><div class="t mc x72 h19 y116 ff5 fsf fc4 sc0 ls69 ws1">Ai<span class="_ _4"></span>n_7/8</div><div class="t mc x16 h19 y117 ff5 fsf fc4 sc0 ls6c ws1">AUDIO_INT</div><div class="t mc x73 h19 y118 ff5 fsf fc4 sc0 ls1 ws1">GRP1_EN/DIS</div><div class="t mc x73 h19 y119 ff5 fsf fc4 sc0 ls1 ws1">GRP2_EN/DIS</div><div class="t mb x74 h18 y11a ff5 fse fc4 sc0 ls63 ws1">HANC/</div><div class="t mb x75 h18 y11b ff5 fse fc4 sc0 ls1 ws1">VANC</div><div class="t mb x76 h18 y11c ff5 fse fc4 sc0 ls1 ws1">Blanking</div><div class="t mb x77 h18 y11d ff5 fse fc4 sc0 ls63 ws56">PLL wit<span class="_ _4"></span>h Low Noise</div><div class="t mb x78 h18 y11e ff5 fse fc4 sc0 ls1 ws1">VCO </div><div class="t mb x79 h18 y11f ff5 fse fc4 sc0 ls1 ws1">Narrow BW PLL</div><div class="t mc x7a h19 y120 ff5 fsf fc4 sc0 ls6d ws1">LOCKED</div><div class="t md x7b h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">DVB_ASI</div><div class="t mc x7c h19 y122 ff5 fsf fc4 sc0 ls68 ws1">NRZ/NRZI</div><div class="t mc x7d h19 y123 ff5 fsf fc4 sc0 ls1 ws1">SMPTE</div><div class="t mc x7c h19 y124 ff5 fsf fc4 sc0 ls69 ws1">Scrambler</div><div class="t me x6b h1a y125 ff5 fs10 fc4 sc0 ls1 ws1">LF</div><div class="t me x7e h1a y125 ff5 fs10 fc4 sc0 ls6e ws1">VBG</div><div class="t me x7f h1a y125 ff5 fs10 fc4 sc0 ls1 ws1">RATE_SEL[1:0]</div><div class="t mc x80 h19 y126 ff5 fsf fc4 sc0 ls6f ws1">CD_VDD</div><div class="t mc x80 h19 y127 ff5 fsf fc4 sc0 ls6f ws1">CD_GND</div><div class="t md x81 h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">CORE_VDD</div><div class="t md x6a h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">CORE_GND</div><div class="t md x82 h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">IO_VDD</div><div class="t md x78 h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">IO_GND</div><div class="t md x83 h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">RESET</div><div class="t md x84 h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">STANDBY</div><div class="t mc x85 h19 y128 ff5 fsf fc4 sc0 ls1 ws1">20BIT/10BIT</div><div class="t mc x73 h19 y129 ff5 fsf fc4 sc0 ls1 ws1">ANC_BLANK</div><div class="t mc x80 h19 y12a ff5 fsf fc4 sc0 ls1 ws1">PLL_VDD</div><div class="t mc x80 h19 y12b ff5 fsf fc4 sc0 ls1 ws1">PLL_GND</div><div class="t mc x80 h19 y12c ff5 fsf fc4 sc0 ls70 ws1">AVDD</div><div class="t mc x80 h19 y12d ff5 fsf fc4 sc0 ls70 ws1">AGND</div><div class="t mc x80 h19 y12e ff5 fsf fc4 sc0 ls71 ws1">VCO_VDD</div><div class="t mc x80 h19 y12f ff5 fsf fc4 sc0 ls71 ws1">VCO_GND</div><div class="t md x86 h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">IOPROC_EN/DIS</div><div class="t md x6e h1a y121 ff5 fs10 fc4 sc0 ls1 ws1">SMPTE_BYPASS</div><div class="t mb x5e h18 y130 ff5 fse fc4 sc0 ls1 ws1">SMPTE ST 425</div><div class="t mb x87 h18 y131 ff5 fse fc4 sc0 ls1 ws1">Level A to Level B </div><div class="t mf x88 h1b y132 ff5 fs11 fc4 sc0 ls72 ws57">10<span class="_ _4"></span>80p 50/60 4:2:2 10-bit</div><div class="t mb x47 h18 y130 ff5 fse fc4 sc0 ls1 ws1">SMPTE ST 352</div><div class="t mb x89 h18 y131 ff5 fse fc4 sc0 ls1 ws1">Generation and</div><div class="t mb x50 h18 y133 ff5 fse fc4 sc0 ls1 ws1">Insertion </div><div class="t mb x8a h18 y134 ff5 fse fc4 sc0 ls1 ws1">3G/HD/SD</div><div class="t mb x8b h18 y135 ff5 fse fc4 sc0 ls1 ws1">Audio</div><div class="t mb x8c h18 y136 ff5 fse fc4 sc0 ls1 ws1">Embedding</div><div class="t mb x8d h18 y137 ff5 fse fc4 sc0 ls73 ws1">GSPI</div><div class="t mb x8e h18 y138 ff5 fse fc4 sc0 ls74 ws1">Host</div><div class="t mb x8f h18 y139 ff5 fse fc4 sc0 ls1 ws1">Interface </div><div class="t md x66 h1a y13a ff5 fs10 fc4 sc0 ls1 ws1">CS_TMS</div><div class="t md x90 h1a y13b ff5 fs10 fc4 sc0 ls1 ws1">SCLK_TCK</div><div class="t md x91 h1a y13c ff5 fs10 fc4 sc0 ls1 ws1">SDIN_TDI</div><div class="t md x64 h1a y13a ff5 fs10 fc4 sc0 ls1 ws1">SDOUT_TDO</div><div class="t mb x92 h18 y138 ff5 fse fc4 sc0 ls75 ws1">JTAG</div><div class="t mb x93 h18 y139 ff5 fse fc4 sc0 ls1 ws1">Controller</div><div class="t md x94 h1a y13a ff5 fs10 fc4 sc0 ls1 ws1">TMS</div><div class="t md x95 h1a y13a ff5 fs10 fc4 sc0 ls1 ws1">TDI</div><div class="t md x96 h1a y13c ff5 fs10 fc4 sc0 ls1 ws1">TDO</div><div class="t md x97 h1a y13c ff5 fs10 fc4 sc0 ls1 ws1">JTAG/HOST</div><div class="t md x98 h1a y13a ff5 fs10 fc4 sc0 ls1 ws1">TCK</div><div class="t m10 x2b h1c y13d ff5 fs12 fc4 sc0 ls1 ws58">Dedicated JTAG pins</div><div class="t m10 x99 h1c y13e ff5 fs12 fc4 sc0 ls1 ws1">Shared JTAG and GSPI pins</div><div class="t m10 x9a h1c y13f ff5 fs12 fc4 sc0 ls1 ws58">(for drop-in compatibility</div><div class="t m10 x9b h1c y140 ff5 fs12 fc4 sc0 ls1 ws1">with GS1572/82)</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/638f674197bc301588149cdc/bg4.jpg"><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls2 ws2">GS2972 3G/HD/SD-SDI Serializer with Complete </div><div class="t m0 x3 h2 y3 ff1 fs0 fc0 sc0 ls3 ws3">SMPTE Audio & Video Support</div><div class="t m0 x3 h2 y4 ff1 fs0 fc0 sc0 ls1 ws4">Final Data Sheet<span class="_ _0"> </span>Rev. 9</div><div class="t m0 x3 h2 y5 ff1 fs0 fc0 sc0 ls4 ws5">GENDOC-047479<span class="_ _1"> </span>September 2013</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">4 of 125</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h6 y9 ff3 fs3 fc1 sc0 ls9 ws1">www.semtech.com</div><div class="t m0 x3 h7 y7a ff2 fs4 fc0 sc0 ls60 ws4f">Revision History</div><div class="t m0 x42 h17 y141 ff1 fsd fc0 sc0 ls76 ws1">Ve<span class="_ _8"></span>r<span class="_ _8"></span>s<span class="_ _3"></span>i<span class="_ _8"></span>o<span class="_ _8"></span>n<span class="_ _f"> </span><span class="ls77">ECO<span class="_ _10"> </span><span class="ls78">PCN<span class="_ _11"> </span><span class="ls79">Date<span class="_ _12"> </span><span class="ls7a ws59">Changes and/o<span class="_ _3"></span>r Modifi</span><span class="ff6 ls1">c</span><span class="ls7b">ations</span></span></span></span></div><div class="t m0 x53 h2 y142 ff5 fs0 fc0 sc0 ls7c ws1">9<span class="_ _13"> </span>01480<span class="ff7 ls1">6<span class="_ _f"> </span><span class="ff5">–<span class="_ _14"> </span></span>S</span><span class="ls7d">eptem<span class="ff7 ls1">b</span></span><span class="ws5a">er 2013<span class="_ _b"> </span>Up</span><span class="ff7 ls1">d</span><span class="ls7e ws5b">ates throu</span><span class="ff7 ls1">g</span><span class="ls7f ws5c">hout the </span><span class="ff7 ls1">d<span class="ff5">o</span>c</span><span class="ls80">ument.</span></div><div class="t m0 x53 h2 y143 ff5 fs0 fc0 sc0 ls7c ws1">8<span class="_ _13"> </span>011355<span class="_ _f"> </span>–<span class="_ _15"> </span>Fe<span class="ff7 ls1">b</span><span class="ls81 ws5d">ruary 2013<span class="_ _16"> </span>Up</span><span class="ff7 ls1">d</span><span class="ls82">ate<span class="ff7 ls1">d</span><span class="ls7d"> to the <span class="ff7 ls1">S</span></span></span>emte<span class="ff7 ls1">c</span><span class="ls83 ws5e">h T<span class="_ _4"></span>emplate.</span></div><div class="t m0 x53 h2 y144 ff5 fs0 fc0 sc0 ls7c ws1">7<span class="_ _13"> </span>155820<span class="_ _17"> </span>5<span class="ff7 ls1">6</span><span class="ls84">554<span class="_ _18"> </span>Fe<span class="ff7 ls1">b</span><span class="ls85 ws5f">ruary 2011</span></span></div><div class="t m0 x9c h2 y145 ff5 fs0 fc0 sc0 ls1 ws1">A<span class="ff7 ls80">dd</span>e<span class="ff7">d</span><span class="ls86 ws60"> se</span><span class="ff7">c</span><span class="ls85">tion <span class="fc1 ls7d">4.7.22.2 Blankin<span class="ff7 ls1">g</span><span class="ls87 ws61"> Values Followin</span><span class="ff7 ls1">g</span><span class="ls88 ws62"> Au</span><span class="ff7 ls1">d</span><span class="ls89">io </span></span></span></div><div class="t m0 x9c h2 y146 ff5 fs0 fc1 sc0 ls87 ws63">Data Pa<span class="ff7 ls1 ws1">c</span><span class="ls0 ws0">ket Insertion<span class="fc0 ls1 ws1">.</span></span></div><div class="t m0 x53 h2 y147 ff7 fs0 fc0 sc0 ls1 ws1">6<span class="_ _13"> </span><span class="ff5 ls7c">155</span>6<span class="ff5 ls7c">08<span class="_ _f"> </span>–<span class="_ _19"> </span></span>J<span class="ff5 ls87 ws63">anuary 2011</span></div><div class="t m0 x9c h2 y148 ff7 fs0 fc0 sc0 ls1 ws1">C<span class="ff5 ls7f">larifie</span>d<span class="ff5 ls82 ws64"> the fun</span>c<span class="ff5 ls8a ws65">tion of the A</span><span class="ls8b">CS<span class="ff5 ls8c">_RE</span></span>G<span class="ff5 ls84">EN<span class="_ _4"></span> <span class="ff7 ls1">b</span><span class="ls87 ws63">it in </span></span></div><div class="t m0 x9c h2 y149 ff7 fs0 fc1 sc0 ls1 ws1">S<span class="ff5">e</span>c<span class="ff5 ws4">tion 4.7.11<span class="fc0 ws1"> <span class="fc1 ls8d">Au</span></span></span>d<span class="ff5 ls7d">io </span>C<span class="ff5 ls80">hannel </span>S<span class="ff5 ls8e">tatus<span class="fc0 ls1">.</span></span></div><div class="t m0 x53 h2 y14a ff5 fs0 fc0 sc0 ls7c ws1">5<span class="_ _13"> </span>155080<span class="_ _17"> </span>5<span class="ff7 ls1">6</span><span class="ls84">059<span class="_ _1a"> </span>O<span class="ff7 ls1">c</span><span class="ls86">to<span class="ff7 ls1">b</span><span class="ls87 ws63">er 2010</span></span></span></div><div class="t m0 x9c h2 y14b ff5 fs0 fc0 sc0 ls8c ws1">Revise<span class="ff7 ls1">d</span><span class="ls8f ws66"> power ratin<span class="_ _3"></span></span><span class="ff7 ls1">g</span><span class="ls7f ws5c"> in stan</span><span class="ff7 ls8b">db</span><span class="ws67">y mo</span><span class="ff7 ls1">d</span><span class="ls3 ws3">e. Do</span><span class="ff7 ls1">c</span><span class="ls90">umente<span class="ff7 ls1">d<span class="ff5"> </span></span></span></div><div class="t m0 x9c h1d y14a ff7 fs0 fc0 sc0 ls80 ws1">CS</div><div class="t m0 x9a h2 y14c ff5 fs0 fc0 sc0 ls91 ws1">UM <span class="ff7 ls1">b</span><span class="ls4 ws5">ehaviour in </span><span class="ff7 fc1 ls1">S<span class="ff5">e</span>c<span class="ff5 ls92 ws68">tion 4.8</span></span><span class="ls7d">, <span class="ff7 fc1 ls1">S<span class="ff5">e</span>c<span class="ff5 ws4">tion 4.9.4</span></span><span class="ls0 ws0"> an<span class="_ _3"></span></span><span class="ff7 ls1">d<span class="ff5"> <span class="fc1 ls93">Vi</span></span><span class="fc1">d<span class="ff5 ls94">eo </span></span></span></span></div><div class="t m0 x9c h2 y14d ff7 fs0 fc1 sc0 ls1 ws1">C<span class="ff5 ls7d">ore </span>C<span class="ff5 ls8c">onfi</span>g<span class="ff5 ls7d">uration an</span>d<span class="ff5"> </span>S<span class="ff5 ls95 ws69">tatus Re</span>g<span class="ff5 ls85">isters<span class="fc0 ls1">.</span></span></div><div class="t m0 x53 h2 y14e ff5 fs0 fc0 sc0 ls7c ws1">4<span class="_ _13"> </span>153717<span class="_ _f"> </span>–<span class="_ _1b"> </span>Mar<span class="ff7 ls1">c</span><span class="ls96 ws6a">h 2010</span></div><div class="t m0 x9c h2 y14f ff5 fs0 fc0 sc0 ls88 ws1">Up<span class="ff7 ls1">d</span><span class="ls81 ws6b">ates throu</span><span class="ff7 ls1">g</span><span class="ls97 ws6c">hout entire </span><span class="ff7 ls1">d<span class="ff5">o</span>c</span><span class="ls80 ws6d">ument. A</span><span class="ff7 ls8b">dd</span><span class="ls1">e<span class="ff7">d</span> <span class="_ _4"></span><span class="fc1 ls8c">Fi<span class="ff7 ls1">g</span><span class="ls90 ws6e">ure 4-2</span><span class="fc0 ls7d">, </span></span></span></div><div class="t m0 x9c h2 y150 ff5 fs0 fc1 sc0 ls8c ws1">Fi<span class="ff7 ls1">g</span><span class="ls90 ws6e">ure 4-3<span class="fc0 ls7c ws6f"> an<span class="ff7 ls1 ws1">d<span class="ff5"> </span></span></span></span>Fi<span class="ff7 ls1">g</span><span class="ls98 ws70">ur<span class="_ _4"></span>e 4-4<span class="fc0 ls7d ws1">. <span class="_ _4"></span><span class="ff7 ls1">C<span class="ff5 ls7e">orre</span>c<span class="ff5 ls91 ws71">tion to re</span>g<span class="ff5 ls7f ws72">isters 040h to </span></span></span></span></div><div class="t m0 x9c h2 y151 ff5 fs0 fc0 sc0 ls3 ws3">13Fh in <span class="fc1 ls7c ws1">Ta<span class="ff7 ls1">b<span class="ff5 ws4">le 4-34: Vi</span>d</span><span class="ls94">eo <span class="ff7 ls1">C</span><span class="ls7d">ore <span class="ff7 ls1">C<span class="_ _3"></span></span><span class="ls99">onfi<span class="ff7 ls1">g<span class="ff5 ws4">uration an</span>d<span class="ff5"> </span>S<span class="_"> </span></span><span class="ls91">tatus </span></span></span></span></span></div><div class="t m0 x9c h2 y152 ff5 fs0 fc1 sc0 ls80 ws1">Re<span class="ff7 ls1">g</span><span class="ls85">isters<span class="fc0 ls1">.</span></span></div><div class="t m0 x53 h2 y153 ff5 fs0 fc0 sc0 ls7c ws1">3<span class="_ _13"> </span>152220<span class="_ _f"> </span>–<span class="_ _1c"> </span><span class="ff7 ls1">J</span><span class="ls9a ws73">uly 2009</span></div><div class="t m0 x9c h2 y154 ff5 fs0 fc0 sc0 ls88 ws1">Up<span class="ff7 ls1">d</span><span class="ls82">ate<span class="ff7 ls1">d</span><span class="ls91 ws74"> Devi</span><span class="ff7 ls1">c</span><span class="ws64">e Laten</span><span class="ff7 ls1">c</span><span class="ls8c ws67">y num</span><span class="ff7 ls1">b</span><span class="ls97 ws75">ers in </span></span></div><div class="t m0 x9d h2 y155 ff5 fs0 fc1 sc0 ls7c ws5a">2.4 A<span class="ff7 ls1 ws1">C</span><span class="ls0 ws0"> Ele<span class="ff7 ls1 ws1">c<span class="ff5 ls86">tri</span>c</span><span class="ws1">al </span></span></div><div class="t m0 x9c h2 y156 ff7 fs0 fc1 sc0 ls1 ws1">C<span class="ff5 ls87">hara</span>c<span class="ff5 ls9a">teristi</span>c<span class="ff5">s<span class="fc0 ws4">. Up</span></span><span class="fc0">d<span class="ff5 ls7f ws5c">ates to <span class="fc1 ls7c ws5a">4.8 AN</span></span></span>C<span class="ff5 ls0 ws0"> Data Insertion<span class="fc0 ls7d ws1">. </span></span></div><div class="t m0 x9c h2 y157 ff5 fs0 fc0 sc0 ls80 ws1">Repla<span class="ff7 ls1">c<span class="ff5">e</span>d<span class="ff5"> <span class="fc1 ls97 ws75">7.3 Markin</span></span><span class="fc1">g<span class="ff5 ls3 ws3"> Dia</span>g<span class="ff5 ls82">ram</span></span><span class="ff5">.</span></span></div><div class="t m0 x53 h2 y158 ff5 fs0 fc0 sc0 ls7c ws1">2<span class="_ _13"> </span>151320<span class="_ _f"> </span><span class="ff4 ls1">−<span class="_ _1d"> </span><span class="ff7">J</span></span><span class="ls87 ws63">anuary 2009</span></div><div class="t m0 x9c h2 y159 ff7 fs0 fc0 sc0 ls1 ws1">C<span class="ff5 ls7e">orre</span>c<span class="ff5 ls87 ws63">tion to timin</span>g<span class="ff5 ls7c ws5a"> values in <span class="fc1 ws1">Ta</span></span><span class="fc1">b<span class="ff5 ls4 ws5">le 4-1: </span><span class="ls88">GS<span class="ff5 ls7d">2972 Di<span class="_ _3"></span></span></span>g<span class="ff5 ls0">ital </span></span></div><div class="t m0 x9c h2 y15a ff5 fs0 fc1 sc0 ls88 ws76">Input A<span class="ff7 ls1 ws1">C</span><span class="ls0 ws0"> Ele<span class="ff7 ls1 ws1">c<span class="ff5 ls86">tri</span>c<span class="ff5 ls7c">al </span>C<span class="ff5 ls99">hara</span>c<span class="_ _3"></span><span class="ff5 ls8e">terist<span class="_ _3"></span>i</span>c<span class="ff5">s<span class="fc0">.</span></span></span></span></div><div class="t m0 x53 h2 y15b ff5 fs0 fc0 sc0 ls7c ws1">1<span class="_ _13"> </span>150803<span class="_ _f"> </span><span class="ff4 ls1">−<span class="_ _1e"> </span></span><span class="ls8d">De<span class="ff7 ls1">c</span></span>em<span class="ff7 ls1">b</span><span class="ls87 ws63">er 2008<span class="_ _1f"> </span></span><span class="ff7 ls1">C</span><span class="ls3">onverte<span class="ff7 ls1">d</span><span class="ls9b ws77"> to Data </span><span class="ff7 ls1">S</span><span class="ws3">heet. Up</span><span class="ff7 ls1">d</span><span class="ls97 ws75">ates to all se</span><span class="ff7 ls1">c</span><span class="ls85">tions.</span></span></div><div class="t m0 x53 h2 y15c ff5 fs0 fc0 sc0 ls7c ws1">0<span class="_ _13"> </span>150717<span class="_ _f"> </span>–<span class="_ _20"> </span>O<span class="ff7 ls1">c</span><span class="ls86">to<span class="ff7 ls1">b</span><span class="ls87 ws63">er 2008<span class="_ _21"> </span></span><span class="ff7 ls1">C</span><span class="ls3">onverte<span class="ff7 ls1">d</span><span class="ls7d"> to Preliminary Data <span class="ff7 ls1">S</span><span class="ls92">heet.</span></span></span></span></div><div class="t m0 x53 h2 y15d ff5 fs0 fc0 sc0 ls7c ws1">D<span class="_ _22"> </span>149428<span class="_ _f"> </span>–<span class="_ _22"> </span>Au<span class="ff7 ls1">g</span><span class="ls7e ws5b">ust 2008</span></div><div class="t m0 x9c h2 y15e ff5 fs0 fc0 sc0 ls88 ws1">Up<span class="ff7 ls1">d</span><span class="ls82">ate<span class="ff7 ls1">d<span class="ff5"> <span class="fc1 ls9c">Typi</span></span><span class="fc1">c<span class="ff5 ls90 ws78">al Appli</span></span></span></span></div><div class="t m0 x9e h2 y15f ff7 fs0 fc1 sc0 ls1 ws1">c<span class="ff5 ls88">ation </span>C<span class="ff5 ls7d">ir</span>c<span class="ff5 ls89">uit<span class="fc0 ls88 ws79">. Applie</span></span><span class="fc0">d<span class="ff5 ls82 ws7a"> new format </span></span></div><div class="t m0 x9c h2 y160 ff5 fs0 fc0 sc0 ls82 ws64">to the <span class="ff7 ls1 ws1">d<span class="ff5">o</span>c</span><span class="ls96 ws6a">ument. Up<span class="ff7 ls1 ws1">d</span><span class="ls7e ws5b">ates to all se<span class="ff7 ls1 ws1">c<span class="ff5 ls85">tions.</span></span></span></span></div><div class="t m0 x53 h2 y161 ff7 fs0 fc0 sc0 ls1 ws1">C<span class="_ _13"> </span><span class="ff5 ls7c">148810<span class="_ _f"> </span>–<span class="_ _15"> </span>Fe</span>b<span class="ff5 ls81 ws5d">ruary 2008<span class="_ _16"> </span>Up</span>d<span class="ff5 ls97 ws75">ates to all se</span>c<span class="ff5 ls85">tions.</span></div><div class="t m0 x53 h2 y162 ff5 fs0 fc0 sc0 ls7c ws1">B<span class="_ _13"> </span>148770<span class="_ _f"> </span>–<span class="_ _1e"> </span>De<span class="ff7 ls1">c</span>em<span class="ff7 ls1">b<span class="_ _3"></span></span><span class="ws5a">er 2007<span class="_ _1f"> </span>Up</span><span class="ff7 ls1">d</span><span class="ls97 ws75">ates an</span><span class="ff7 ls1">d</span><span class="ls9a ws73"> revise</span><span class="ff7 ls1">d<span class="ff5"> </span></span><span class="fc1 ws5a">5.1 Typi<span class="ff7 ls1 ws1">c</span><span class="ls88 ws76">al Appli<span class="ff7 ls1 ws1">c</span><span class="ws1">ation <span class="ff7 ls1">C<span class="_ _3"></span></span><span class="ls7d">ir<span class="ff7 ls1">c</span><span class="ls89">uit</span></span></span></span></span><span class="ls1">.</span></div><div class="t m0 x53 h2 y163 ff5 fs0 fc0 sc0 ls7c ws1">A<span class="_ _22"> </span>147987<span class="_ _f"> </span>–<span class="_ _23"> </span>De<span class="ff7 ls1">c</span>em<span class="ff7 ls1">b</span><span class="ls87 ws63">er 2007<span class="_ _1f"> </span>New Do</span><span class="ff7 ls1">c</span><span class="ls8c">ument.</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/638f674197bc301588149cdc/bg5.jpg"><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls2 ws2">GS2972 3G/HD/SD-SDI Serializer with Complete </div><div class="t m0 x3 h2 y3 ff1 fs0 fc0 sc0 ls3 ws3">SMPTE Audio & Video Support</div><div class="t m0 x3 h2 y4 ff1 fs0 fc0 sc0 ls1 ws4">Final Data Sheet<span class="_ _0"> </span>Rev. 9</div><div class="t m0 x3 h2 y5 ff1 fs0 fc0 sc0 ls4 ws5">GENDOC-047479<span class="_ _1"> </span>September 2013</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">5 of 125</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h6 y9 ff3 fs3 fc1 sc0 ls9 ws1">www.semtech.com</div><div class="t m0 x3 h3 y164 ff2 fs1 fc0 sc0 ls9d ws1">Contents</div><div class="t m0 x3 h1e y165 ff3 fsd fc0 sc0 ls9e ws7b">Key Features<span class="_ _d"> </span>...................<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>......<span class="ws1">.....<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>....<span class="_ _24"></span>1</span></div><div class="t m0 x3 h1e y166 ff3 fsd fc0 sc0 ls9f ws1">Applications<span class="_ _8"></span>.......<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.....<span class="ls9e">....<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>....<span class="_ _24"></span>1</span></div><div class="t m0 x3 h1e y167 ff3 fsd fc0 sc0 ls9f ws1">Description<span class="_ _24"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>..<span class="ls9e">.......<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="_ _8"></span>2</span></div><div class="t m0 x3 h1e y168 ff3 fsd fc0 sc0 lsa0 ws7c">Functional Block Diagram<span class="_"> </span>.................<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span><span class="ls9e ws1">...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _24"></span>3</span></div><div class="t m0 x3 h1e y169 ff3 fsd fc0 sc0 lsa1 ws7d">Revision History<span class="_ _d"> </span>..............<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>..<span class="ls9e ws1">....<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _24"></span>4</span></div><div class="t m0 x3 h1e y16a ff3 fsd fc0 sc0 ls9e ws7e">1. Pin Out<span class="_ _3"></span>....<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="ws1">..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>.<span class="_"> </span>10</span></div><div class="t m0 x42 h1e y16b ff3 fsd fc0 sc0 ls9f ws7f">1.1 Pin Assignment <span class="_ _3"></span>....<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="ls9e ws1">.....<span class="_ _3"></span>...........<span class="_ _3"></span>...<span class="_"> </span>10</span></div><div class="t m0 x42 h1e y16c ff3 fsd fc0 sc0 ls9f ws7f">1.2 Pin Descriptions<span class="_ _3"></span> <span class="_ _d"> </span>...............<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span><span class="ls9e ws1">..........<span class="_ _3"></span>........<span class="_ _3"></span>.<span class="_"> </span>11</span></div><div class="t m0 x3 h1e y16d ff3 fsd fc0 sc0 lsa1 ws80">2. Electrical Chara<span class="_ _3"></span>cteristics<span class="_"> </span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>....<span class="ls9e ws1">...<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="_"> </span>20</span></div><div class="t m0 x42 h1e y16e ff3 fsd fc0 sc0 lsa1 ws7d">2.1 Absolute Maximum Ratings <span class="_ _8"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>....<span class="ls9e ws1">..<span class="_ _3"></span>...<span class="_"> </span>20</span></div><div class="t m0 x42 h1e y16f ff3 fsd fc0 sc0 ls8 ws81">2.2 Recommended Operating Conditions <span class="_ _8"></span>.....<span class="lsa2 ws1">...........<span class="_ _3"></span><span class="lsa3">..........</span>............................................<span class="_ _3"></span><span class="lsa4">.........<span class="ls1">.....<span class="_"> </span>20</span></span></span></div><div class="t m0 x42 h1e y170 ff3 fsd fc0 sc0 lsa5 ws82">2.3 DC Electrical Characteristics <span class="_ _d"> </span>..<span class="_ _3"></span>....<span class="ls9e ws1">.......<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="lsa6">........<span class="_"> </span>21</span></span></div><div class="t m0 x42 h1e y171 ff3 fsd fc0 sc0 lsa7 ws83">2.4 AC Electrical Characte<span class="_ _3"></span>rist<span class="ls9f ws84">ics ........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>....<span class="lsa6 ws1">........<span class="_"> </span>2<span class="_ _4"></span>3</span></span></div><div class="t m0 x3 h1e y172 ff3 fsd fc0 sc0 lsa8 ws85">3. Input/Out<span class="_ _3"></span>put Circuits<span class="_"> </span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="ls9e ws1">......<span class="_ _3"></span>...........<span class="_ _3"></span>.......<span class="_"> </span>26</span></div><div class="t m0 x3 h1e y173 ff3 fsd fc0 sc0 lsa8 ws85">4. Detailed De<span class="_ _3"></span>scription<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="ls9e ws1">...<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="_"> </span>30</span></div><div class="t m0 x42 h1e y174 ff3 fsd fc0 sc0 lsa1 ws7d">4.1 Functional Overview <span class="_ _3"></span>......<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...<span class="ls9e ws1">....<span class="_ _3"></span>.........<span class="_"> </span>30</span></div><div class="t m0 x42 h1e y175 ff3 fsd fc0 sc0 ls9f ws86">4.2 Parallel<span class="_ _3"></span> Data Input<span class="_ _3"></span>s .........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...<span class="ls9e ws1">........<span class="_ _3"></span>.........<span class="_"> </span>31</span></div><div class="t m0 x12 h1e y176 ff3 fsd fc0 sc0 lsa1 ws80">4.2.1 Paralle<span class="_ _3"></span>l Input in SMPTE <span class="_ _3"></span>Mode<span class="_ _3"></span>.<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...<span class="_"> </span>33</div><div class="t m0 x12 h1e y177 ff3 fsd fc0 sc0 lsa1 ws80">4.2.2 Paralle<span class="_ _3"></span>l Input in D<span class="_ _3"></span>VB-ASI Mode<span class="_ _8"></span>....<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.....<span class="_"> </span>33</div><div class="t m0 x12 h1e y178 ff3 fsd fc0 sc0 lsa9 ws80">4.2.3 Paralle<span class="_ _3"></span>l Input in D<span class="_ _3"></span>ata-Through Mode<span class="_ _8"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="_"> </span>34</div><div class="t m0 x12 h1e y179 ff3 fsd fc0 sc0 lsa1 ws80">4.2.4 Paralle<span class="_ _3"></span>l Input Clock (PCL<span class="_ _3"></span>K)<span class="_ _d"> </span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.......<span class="_"> </span>34</div><div class="t m0 x42 h1e y17a ff3 fsd fc0 sc0 ls9f ws7f">4.3 SMPTE Mode <span class="_"> </span>............<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="ls9e ws1">.<span class="_ _3"></span>.........<span class="_ _3"></span>.........<span class="_"> </span>35</span></div><div class="t m0 x12 h1e y17b ff3 fsd fc0 sc0 lsa8 ws52">4.3.1 H:V:F Timing<span class="_"> </span>................<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>..<span class="lsa6 ws1">..........<span class="_ _d"> </span>35</span></div><div class="t m0 x12 h1e y17c ff3 fsd fc0 sc0 ls9f ws7f">4.3.2 CEA 861 Timin<span class="_ _3"></span>g<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>.....<span class="ls9e ws1">....<span class="_ _3"></span>...<span class="_"> </span>38</span></div><div class="t m0 x42 h1e y17d ff3 fsd fc0 sc0 ls9f ws7f">4.4 DVB-ASI Mode <span class="_"> </span>......<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="ls9e ws1">........<span class="_ _3"></span>........<span class="_ _3"></span>.<span class="_"> </span>44</span></div><div class="t m0 x42 h1e y17e ff3 fsd fc0 sc0 lsa8 ws52">4.5 Data-Through Mode <span class="_"> </span>..............<span class="_ _3"></span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span><span class="ls9e ws1">.......<span class="_ _3"></span>.....<span class="_"> </span>44</span></div><div class="t m0 x42 h1e y17f ff3 fsd fc0 sc0 ls9f ws7f">4.6 Standby Mode <span class="_ _24"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span><span class="ls9e ws1">..........<span class="_ _3"></span>........<span class="_ _3"></span>.<span class="_"> </span>44</span></div><div class="t m0 x42 h1e y180 ff3 fsd fc0 sc0 ls9f ws7f">4.7 Audio Embedd<span class="_ _3"></span>ing .<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...<span class="ls9e ws1">......<span class="_ _3"></span>.........<span class="_"> </span>45</span></div><div class="t m0 x12 h1e y181 ff3 fsd fc0 sc0 lsa8 ws85">4.7.1 Ser<span class="_ _3"></span>ial Audio Data <span class="_ _3"></span>Inputs<span class="_ _d"> </span>..................<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.......<span class="_"> </span><span class="lsaa ws1">45</span></div><div class="t m0 x12 h1e y182 ff3 fsd fc0 sc0 lsa9 ws87">4.7.2 Seri<span class="_ _3"></span>al Audio Data Format<span class="_ _3"></span> Support<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.......<span class="_"> </span>47</div><div class="t m0 x12 h1e y183 ff3 fsd fc0 sc0 ls9e ws7b">4.7.3 3G Mode<span class="_ _3"></span>.......<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>......<span class="ws1">..<span class="_ _3"></span>.........<span class="_ _3"></span>...<span class="_"> </span>49</span></div><div class="t m0 x12 h1e y184 ff3 fsd fc0 sc0 ls9f ws7f">4.7.4 HD Mode<span class="_ _3"></span>......<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.....<span class="ls9e ws1">....<span class="_ _3"></span>.........<span class="_"> </span>49</span></div><div class="t m0 x12 h1e y185 ff3 fsd fc0 sc0 ls9f ws7f">4.7.5 SD Mode<span class="_ _3"></span>.....<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>......<span class="ls9e ws1">..<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="_"> </span>50</span></div><div class="t m0 x12 h1e y186 ff3 fsd fc0 sc0 lsa8 ws52">4.7.6 Audio E<span class="_ _3"></span>mbedding Operating Modes<span class="_"> </span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...<span class="_"> </span>50</div><div class="t m0 x12 h1e y187 ff3 fsd fc0 sc0 ls9e ws7b">4.7.7 Audio Pa<span class="_ _3"></span>cket Detection<span class="_ _24"></span>......<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...<span class="_"> </span><span class="lsaa ws1">51</span></div><div class="t m0 x12 h1e y188 ff3 fsd fc0 sc0 ls9f ws7f">4.7.8 Audio Pa<span class="_ _3"></span>cket Deletion<span class="_ _d"> </span>......<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>..<span class="lsab ws1">.5<span class="_ _25"></span>1</span></div><div class="t m0 x12 h1e y189 ff3 fsd fc0 sc0 ls9f ws7f">4.7.9 Audio Pa<span class="_ _3"></span>cket Detection<span class="_ _3"></span> and Deletion<span class="_"> </span>..............<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>.......<span class="_"> </span>51</div><div class="t m0 x12 h1e y18a ff3 fsd fc0 sc0 lsa1 ws7d">4.7.10 Audio Mute (Def<span class="_ _3"></span>ault Off)<span class="_ _24"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_"> </span>52</div><div class="t m0 x12 h1e y18b ff3 fsd fc0 sc0 lsa8 ws52">4.7.11 Audio Channe<span class="_ _3"></span>l Status<span class="_ _d"> </span>................<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.<span class="_"> </span><span class="lsaa ws1">53</span></div><div class="t m0 x12 h1e y18c ff3 fsd fc0 sc0 lsa1 ws7d">4.7.12 Audio Crosspoint<span class="_ _3"></span>......<span class="_ _3"></span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>....<span class="ls9e ws1">....<span class="_ _3"></span>.<span class="_"> </span>54</span></div><div class="t m0 x12 h1e y18d ff3 fsd fc0 sc0 lsa1 ws7d">4.7.13 Audio Word Clock<span class="_"> </span>................<span class="_ _3"></span>...........<span class="_ _3"></span>........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>.....<span class="lsa6 ws1">..<span class="_"> </span>55</span></div><div class="t m0 x12 h1e y18e ff3 fsd fc0 sc0 lsa1 ws7d">4.7.14 Channe<span class="_ _3"></span>l & Group Activation<span class="_ _d"> </span>...................<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.....<span class="_"> </span>55</div><div class="t m0 x12 h1e y18f ff3 fsd fc0 sc0 lsa8 ws52">4.7.15 Audio FIFO - SD<span class="_ _24"></span>.<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>..........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="lsa6 ws1">......<span class="_"> </span>56</span></div><div class="t m0 x12 h1e y190 ff3 fsd fc0 sc0 lsa8 ws52">4.7.16 Audio FIFO - HD and 3G<span class="_ _8"></span>.......<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>..........<span class="_ _3"></span>.........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>...........<span class="_ _3"></span>.........<span class="_ _3"></span>.......<span class="_"> </span>57</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m7"></div></a><a class="l" rel='nofollow' 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