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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62677ce64f8811599eed1451/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">Q/DKBA </div><div class="t m0 x1 h4 y3 ff2 fs0 fc0 sc0 ls0 ws0">深圳市华为技术有限公司企业标准 </div><div class="t m0 x1 h3 y4 ff1 fs0 fc0 sc0 ls0 ws0">Q/DKBA-Y004-1999 </div><div class="t m0 x1 h4 y5 ff2 fs0 fc0 sc0 ls0 ws0">印制电路板（<span class="ff1">PCB</span>）设计规范 </div><div class="t m0 x1 h3 y6 ff1 fs0 fc0 sc0 ls0 ws0">VER 1.0 </div><div class="t m0 x1 h4 y7 ff1 fs0 fc0 sc0 ls0 ws0">1999-07-30<span class="_ _0"> </span><span class="ff2">发布 </span>1999-08-30<span class="_ _0"> </span><span class="ff2">实施 </span></div><div class="t m0 x1 h4 y8 ff2 fs0 fc0 sc0 ls0 ws0">深 圳 市 华 为 技 术 有 限 公 司 发布 </div><div class="t m0 x1 h4 y9 ff2 fs0 fc0 sc0 ls0 ws0">前 言 </div><div class="t m0 x1 h4 ya ff2 fs0 fc0 sc0 ls0 ws0">本标准根据国家标准印制电路板设计和使用 等标准编制而成。 </div><div class="t m0 x1 h4 yb ff2 fs0 fc0 sc0 ls0 ws0">本标准于<span class="_ _0"> </span><span class="ff1">1998<span class="_ _0"> </span></span>年<span class="_ _0"> </span><span class="ff1">07 </span>月<span class="_ _0"> </span><span class="ff1">30<span class="_ _0"> </span></span>日首次发布。 </div><div class="t m0 x1 h4 yc ff2 fs0 fc0 sc0 ls0 ws0">本标准起草单位： <span class="ff1">CAD<span class="_ _0"> </span></span>研究部、硬件工程室 </div><div class="t m0 x1 h4 yd ff2 fs0 fc0 sc0 ls0 ws0">本标准主要起草人：吴多明 韩朝伦 胡庆虎 龚良忠 张珂 梅泽良 </div><div class="t m0 x1 h4 ye ff2 fs0 fc0 sc0 ls0 ws0">本标准批准人：周代琪 </div><div class="t m0 x1 h4 yf ff2 fs0 fc0 sc0 ls0 ws0">印制电路板（<span class="ff1">PCB</span>）设计规范 </div><div class="t m0 x1 h4 y10 ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff2">适用范围 </span></div><div class="t m0 x1 h4 y11 ff2 fs0 fc0 sc0 ls0 ws0">本《规范》适用于华为公司<span class="_ _0"> </span><span class="ff1">CAD<span class="_ _0"> </span></span>设计的所有印制电路板（简称<span class="_ _0"> </span><span class="ff1">PCB</span>）。 </div><div class="t m0 x1 h4 y12 ff1 fs0 fc0 sc0 ls0 ws0">2. <span class="ff2">引用标准 </span></div><div class="t m0 x1 h4 y13 ff2 fs0 fc0 sc0 ls0 ws0">下列标准包含的条文，通过在本标准中引用而构成本标准的条文。在标准出版时，所示版本均为有效。所</div><div class="t m0 x1 h4 y14 ff2 fs0 fc0 sc0 ls0 ws0">有标准都会被修订，使用本标准的各方应探讨，使用下列标准最新版本的可能性。 </div><div class="t m0 x1 h3 y15 ff1 fs0 fc0 sc0 ls0 ws0">GB 4588.3—88 </div><div class="t m0 x1 h4 y16 ff2 fs0 fc0 sc0 ls0 ws0">印制电路板设计和使用 </div><div class="t m0 x1 h3 y17 ff1 fs0 fc0 sc0 ls0 ws0">Q/DKBA-Y001-1999 </div><div class="t m0 x1 h4 y18 ff2 fs0 fc0 sc0 ls0 ws0">印制电路板<span class="_ _0"> </span><span class="ff1">CAD<span class="_ _0"> </span></span>工艺设计规范 </div><div class="t m0 x1 h4 y19 ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff2">术语 </span></div><div class="t m0 x1 h4 y1a ff1 fs0 fc0 sc0 ls0 ws0">1..1 PCB<span class="ff2">（</span>Print circuit Board)<span class="ff2">：印刷电路板。 </span></div><div class="t m0 x1 h4 y1b ff1 fs0 fc0 sc0 ls0 ws0">1..2 <span class="ff2">原理图：电路原理图，用原理图设计工具绘制的、表达硬件电路中各种器件之间的连接关系的图。 </span></div><div class="t m0 x1 h4 y1c ff1 fs0 fc0 sc0 ls0 ws0">1..3 <span class="ff2">网络表：由原理图设计工具自动生成的、表达元器件电气连接关系的文本文件，一般包含元器件封</span></div><div class="t m0 x1 h4 y1d ff2 fs0 fc0 sc0 ls0 ws0">装、网络列表和属性定义等组成部分。 </div><div class="t m0 x1 h4 y1e ff1 fs0 fc0 sc0 ls0 ws0">1..4 <span class="ff2">布局：</span>PCB<span class="_ _0"> </span><span class="ff2">设计过程中，按照设计要求，把元器件放置到板上的过程。 深圳市华为技术有限公司</span></div><div class="t m0 x1 h4 y1f ff1 fs0 fc0 sc0 ls0 ws0">1999-07-30<span class="_ _0"> </span><span class="ff2">批准 </span></div><div class="t m0 x1 h4 y20 ff1 fs0 fc0 sc0 ls0 ws0">1999-08-30<span class="_ _0"> </span><span class="ff2">实施 </span></div><div class="t m0 x1 h4 y21 ff1 fs0 fc0 sc0 ls0 ws0">1..5 <span class="ff2">仿真：在器件的<span class="_ _0"> </span></span>IBIS MODEL<span class="_ _0"> </span><span class="ff2">或<span class="_ _0"> </span></span>SPICE MODEL<span class="_ _0"> </span><span class="ff2">支持下，利用<span class="_ _0"> </span></span>EDA<span class="_ _0"> </span><span class="ff2">设计工具对<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">的布局、布线</span></div><div class="t m0 x1 h4 y22 ff2 fs0 fc0 sc0 ls0 ws0">效果进行仿真分析，从而在单板的物理实现之前发现设计中存在的<span class="_ _0"> </span><span class="ff1">EMC<span class="_ _0"> </span></span>问题、时序问题和信号完整性问</div><div class="t m0 x1 h4 y23 ff2 fs0 fc0 sc0 ls0 ws0">题，并找出适当的解决方案。 深圳市华为技术有限公司<span class="_ _0"> </span><span class="ff1">1999-07-30<span class="_ _0"> </span></span>批准 </div><div class="t m0 x1 h4 y24 ff1 fs0 fc0 sc0 ls0 ws0">1999-08-30<span class="_ _0"> </span><span class="ff2">实施 </span></div><div class="t m0 x1 h4 y25 ff1 fs0 fc0 sc0 ls0 ws0">II. <span class="ff2">目的 </span></div><div class="t m0 x1 h4 y26 ff1 fs0 fc0 sc0 ls0 ws0">A. <span class="ff2">本规范归定了我司<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">设计的流程和设计原则，主要目的是为<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">设计者提供必须遵循的规则和约定。</span></div><div class="t m0 x1 h4 y27 ff2 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h4 y28 ff1 fs0 fc0 sc0 ls0 ws0">B. <span class="ff2">提高<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">设计质量和设计效率。 </span></div></div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62677ce64f8811599eed1451/bg2.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h4 y29 ff2 fs0 fc0 sc0 ls0 ws0">提高<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>的可生产性、可测试、可维护性。 </div><div class="t m0 x1 h4 y3 ff1 fs0 fc0 sc0 ls0 ws0">III. <span class="ff2">设计任务受理 </span></div><div class="t m0 x1 h4 y2a ff1 fs0 fc0 sc0 ls0 ws0">A. PCB<span class="_ _0"> </span><span class="ff2">设计申请流程 </span></div><div class="t m0 x1 h4 y5 ff2 fs0 fc0 sc0 ls0 ws0">当硬件项目人员需要进行<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>设计时，须在《<span class="ff1">PCB<span class="_ _0"> </span></span>设计投板申请表》中提出投板申请，并经其项目经理</div><div class="t m0 x1 h4 y2b ff2 fs0 fc0 sc0 ls0 ws0">和计划处批准后，流程状态到达指定的<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>设计部门审批，此时硬件项目人员须准备好以下资料： </div><div class="t m0 x1 h4 y7 ff2 fs0 fc0 sc0 ls0 ws0">经过评审的，完全<span class="ff3">正确</span>的原理图，包<span class="ff3">括纸面</span>文件和电<span class="ff3">子</span>件<span class="ff3">；</span> </div><div class="t m0 x1 h4 y8 ff3 fs0 fc0 sc0 ls0 ws0">带<span class="ff2">有<span class="_ _0"> </span><span class="ff1">MRPII<span class="_ _0"> </span></span>元件编</span>码<span class="ff2">的</span>正式<span class="ff2">的<span class="_ _0"> </span><span class="ff1">BOM</span></span>；<span class="ff2"> </span></div><div class="t m0 x1 h4 y9 ff1 fs0 fc0 sc0 ls0 ws0">PCB<span class="_ _0"> </span><span class="ff3">结<span class="ff2">构图，应标明</span>外形尺寸<span class="ff2">、</span>安<span class="ff2">装</span>孔大小及<span class="ff2">定位</span>尺寸<span class="ff2">、接</span>插<span class="ff2">件定位</span>尺寸<span class="ff2">、</span>禁止<span class="ff2">布线</span>区<span class="ff2">等</span>相<span class="ff2">关</span>尺寸；<span class="ff2"> </span></span></div><div class="t m0 x1 h4 ya ff2 fs0 fc0 sc0 ls0 ws0">对于新器件，<span class="ff3">即无<span class="_ _0"> </span><span class="ff1">MRPII<span class="_ _0"> </span></span></span>编<span class="ff3">码</span>的器件，需要提供封装资料<span class="ff3">；</span> </div><div class="t m0 x1 h4 yb ff2 fs0 fc0 sc0 ls0 ws0">以上资料经指定的<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>设计部门审批<span class="ff3">合格</span>并指定<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>设计者后方可<span class="ff3">开始<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span></span>设计。 </div><div class="t m0 x1 h4 yc ff1 fs0 fc0 sc0 ls0 ws0">B. <span class="ff2">理解设计要求并制定设计计划 </span></div><div class="t m0 x1 h4 yd ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff3">仔细<span class="ff2">审</span>读<span class="ff2">原理图，理解电路的工</span>作<span class="ff2">条件。</span>如模拟<span class="ff2">电路的工</span>作频<span class="ff2">率，</span>数字<span class="ff2">电路的工</span>作速度<span class="ff2">等</span>与<span class="ff2">布线要求</span></span></div><div class="t m0 x1 h4 ye ff3 fs0 fc0 sc0 ls0 ws0">相<span class="ff2">关的要</span>素<span class="ff2">。理解电路的</span>基<span class="ff2">本</span>功<span class="ff2">能、在系</span>统<span class="ff2">中的</span>作<span class="ff2">用等</span>相<span class="ff2">关问题。 </span></div><div class="t m0 x1 h4 y2c ff1 fs0 fc0 sc0 ls0 ws0">2. <span class="ff2">在<span class="ff3">与</span>原理图设计者<span class="ff3">充</span>分<span class="ff3">交</span>流的<span class="ff3">基础</span>上，<span class="ff3">确认</span>板上的关<span class="ff3">键</span>网络，<span class="ff3">如</span>电<span class="ff3">源</span>、时<span class="ff3">钟</span>、高<span class="ff3">速总</span>线等，了解其布</span></div><div class="t m0 x1 h4 y2d ff2 fs0 fc0 sc0 ls0 ws0">线要求。理解板上的高<span class="ff3">速</span>器件<span class="ff3">及</span>其布线要求。 </div><div class="t m0 x1 h4 yf ff1 fs0 fc0 sc0 ls0 ws0">3. <span class="ff2">根据《硬件原理图设计规范》的要求，对原理图进行规范性审<span class="ff3">查</span>。 </span></div><div class="t m0 x1 h4 y10 ff1 fs0 fc0 sc0 ls0 ws0">4. <span class="ff2">对于原理图中<span class="ff3">不符合</span>硬件原理图设计规范的<span class="ff3">地</span>方，要明<span class="ff3">确</span>指出，并<span class="ff3">积极协助</span>原理图设计者进行修<span class="ff3">改</span>。 </span></div><div class="t m0 x1 h4 y11 ff1 fs0 fc0 sc0 ls0 ws0">5. <span class="ff2">在<span class="ff3">与</span>原理图设计者<span class="ff3">交</span>流的<span class="ff3">基础</span>上制定出单板的<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">设计计划，<span class="ff3">填写</span>设计<span class="ff3">记录</span>表，计划要包含设计过程</span></div><div class="t m0 x1 h4 y12 ff2 fs0 fc0 sc0 ls0 ws0">中原理图<span class="ff3">输入</span>、布局完成、布线完成、信号完整性分析、<span class="ff3">光</span>绘完成等关<span class="ff3">键检查点</span>的时间要求。设计计划应</div><div class="t m0 x1 h4 y13 ff2 fs0 fc0 sc0 ls0 ws0">由<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>设计者和原理图设计者<span class="ff3">双</span>方<span class="ff3">签字认</span>可。 </div><div class="t m0 x1 h4 y14 ff1 fs0 fc0 sc0 ls0 ws0">6. <span class="ff2">必要时，设计计划应<span class="ff3">征得</span>上<span class="ff3">级</span>主<span class="ff3">管</span>的批准。 </span></div><div class="t m0 x1 h4 y2e ff1 fs0 fc0 sc0 ls0 ws0">IV. <span class="ff2">设计过程 </span></div><div class="t m0 x1 h4 y16 ff1 fs0 fc0 sc0 ls0 ws0">A. <span class="ff3">创建<span class="ff2">网络表 </span></span></div><div class="t m0 x1 h4 y2f ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff2">网络表是原理图<span class="ff3">与<span class="_ _0"> </span></span></span>PCB<span class="_ _0"> </span><span class="ff2">的接<span class="ff3">口</span>文件，</span>PCB<span class="_ _0"> </span><span class="ff2">设计人员应根据所用的原理图和<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">设计工具的<span class="ff3">特</span>性，<span class="ff3">选</span></span></div><div class="t m0 x1 h4 y18 ff2 fs0 fc0 sc0 ls0 ws0">用<span class="ff3">正确</span>的网络表<span class="ff3">格式</span>，<span class="ff3">创建符合</span>要求的网络表。 </div><div class="t m0 x1 h4 y19 ff1 fs0 fc0 sc0 ls0 ws0">2. <span class="ff3">创建<span class="ff2">网络表的过程中，应根据原理图设计工具的</span>特<span class="ff2">性，</span>积极协助<span class="ff2">原理图设计者</span>排除错误<span class="ff2">。</span>保证<span class="ff2">网络表</span></span></div><div class="t m0 x1 h4 y1a ff2 fs0 fc0 sc0 ls0 ws0">的<span class="ff3">正确</span>性和完整性。 </div><div class="t m0 x1 h4 y1b ff1 fs0 fc0 sc0 ls0 ws0">3. <span class="ff3">确<span class="ff2">定器件的封装（</span></span>PCB FOOTPRINT<span class="ff2">）<span class="ff3">．</span> </span></div><div class="t m0 x1 h4 y1c ff1 fs0 fc0 sc0 ls0 ws0">4. <span class="ff3">创建<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">板 </span></div><div class="t m0 x1 h4 y1d ff2 fs0 fc0 sc0 ls0 ws0">根据单板<span class="ff3">结</span>构图或对应的标准板<span class="ff3">框<span class="ff1">, </span>创建<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span></span>设计文件<span class="ff3">；</span> </div><div class="t m0 x1 h4 y1e ff3 fs0 fc0 sc0 ls0 ws0">注意正确选<span class="ff2">定单板</span>坐<span class="ff2">标原</span>点<span class="ff2">的位置，原</span>点<span class="ff2">的设置原则： </span></div><div class="t m0 x1 h4 y1f ff1 fs0 fc0 sc0 ls0 ws0">A. <span class="ff2">单板<span class="ff3">左边</span>和下<span class="ff3">边</span>的<span class="ff3">延长</span>线<span class="ff3">交汇点</span>。 </span></div><div class="t m0 x1 h4 y20 ff1 fs0 fc0 sc0 ls0 ws0">B. <span class="ff2">单板<span class="ff3">左</span>下<span class="ff3">角</span>的<span class="ff3">第</span>一<span class="ff3">个焊盘</span>。 </span></div><div class="t m0 x1 h4 y30 ff2 fs0 fc0 sc0 ls0 ws0">板<span class="ff3">框四</span>周<span class="ff3">倒圆角</span>，<span class="ff3">倒角半径<span class="_ _0"> </span><span class="ff1">5mm</span></span>。<span class="ff3">特殊情况参考结</span>构设计要求。 </div><div class="t m0 x1 h4 y21 ff1 fs0 fc0 sc0 ls0 ws0">B. <span class="ff2">布局 </span></div><div class="t m0 x1 h4 y22 ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff2">根据<span class="ff3">结</span>构图设置板<span class="ff3">框尺寸</span>，按<span class="ff3">结</span>构要<span class="ff3">素</span>布置<span class="ff3">安</span>装<span class="ff3">孔</span>、接<span class="ff3">插</span>件等需要定位的器件，并<span class="ff3">给这些</span>器件<span class="ff3">赋予不</span></span></div><div class="t m0 x1 h4 y23 ff2 fs0 fc0 sc0 ls0 ws0">可<span class="ff3">移</span>动属性。 按工艺设计规范的要求进行<span class="ff3">尺寸</span>标<span class="ff3">注</span>。 </div><div class="t m0 x1 h4 y24 ff1 fs0 fc0 sc0 ls0 ws0">2. <span class="ff2">根据<span class="ff3">结</span>构图和生产<span class="ff3">加</span>工时所须的<span class="ff3">夹</span>持<span class="ff3">边</span>设置印制板的<span class="ff3">禁止</span>布线<span class="ff3">区</span>、<span class="ff3">禁止</span>布局<span class="ff3">区域</span>。根据<span class="ff3">某些</span>元件的<span class="ff3">特</span></span></div><div class="t m0 x1 h4 y31 ff3 fs0 fc0 sc0 ls0 ws0">殊<span class="ff2">要求，设置</span>禁止<span class="ff2">布线</span>区<span class="ff2">。 </span></div><div class="t m0 x1 h4 y32 ff1 fs0 fc0 sc0 ls0 ws0">3. <span class="ff3">综合考虑<span class="_ _0"> </span></span>PCB<span class="_ _0"> </span><span class="ff2">性能和<span class="ff3">加</span>工的效率<span class="ff3">选择加</span>工流程。 </span></div><div class="t m0 x1 h4 y25 ff3 fs0 fc0 sc0 ls0 ws0">加<span class="ff2">工工艺的</span>优选顺<span class="ff2">序为：元件</span>面<span class="ff2">单</span>面贴<span class="ff2">装</span>——<span class="ff2">元件</span>面贴<span class="ff2">、</span>插混<span class="ff2">装（元件</span>面插<span class="ff2">装</span>焊<span class="ff2">接</span>面贴<span class="ff2">装一次</span>波峰<span class="ff2">成</span>型<span class="ff2">）</span></div><div class="t m0 x1 h4 y26 ff3 fs0 fc0 sc0 ls0 ws0">——双面贴<span class="ff2">装</span>——<span class="ff2">元件</span>面贴插混<span class="ff2">装、</span>焊<span class="ff2">接</span>面贴<span class="ff2">装。 </span></div><div class="t m0 x1 h4 y27 ff1 fs0 fc0 sc0 ls0 ws0">4. <span class="ff2">布局<span class="ff3">操作</span>的<span class="ff3">基</span>本原则 </span></div><div class="t m0 x1 h4 y28 ff1 fs0 fc0 sc0 ls0 ws0">A. <span class="ff2">遵照<span class="ff3">“先大</span>后<span class="ff3">小</span>，<span class="ff3">先难</span>后<span class="ff3">易”</span>的布置原则，<span class="ff3">即重</span>要的单元电路、<span class="ff3">核心</span>元器件应当<span class="ff3">优先</span>布局<span class="ff3">．</span> </span></div></div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62677ce64f8811599eed1451/bg3.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h4 y29 ff1 fs0 fc0 sc0 ls0 ws0">B. <span class="ff2">布局中应<span class="ff3">参考</span>原理<span class="ff3">框</span>图，根据单板的主信号流<span class="ff3">向</span>规<span class="ff3">律安排</span>主要元器件<span class="ff3">．</span> </span></div><div class="t m0 x1 h4 y3 ff1 fs0 fc0 sc0 ls0 ws0">C. <span class="ff2">布局应<span class="ff3">尽</span>量<span class="ff3">满足</span>以下要求</span>:<span class="ff3">总<span class="ff2">的连线</span>尽<span class="ff2">可能</span>短<span class="ff2">，关</span>键<span class="ff2">信号线最</span>短</span>;<span class="ff2">高电<span class="ff3">压</span>、<span class="ff3">大</span>电流信号<span class="ff3">与小</span>电流，<span class="ff3">低</span>电<span class="ff3">压</span></span></div><div class="t m0 x1 h4 y2a ff2 fs0 fc0 sc0 ls0 ws0">的<span class="ff3">弱</span>信号完全分<span class="ff3">开<span class="ff1">;</span>模拟</span>信号<span class="ff3">与数字</span>信号分<span class="ff3">开；</span>高<span class="ff3">频</span>信号<span class="ff3">与低频</span>信号分<span class="ff3">开；</span>高<span class="ff3">频</span>元器件的间<span class="ff3">隔</span>要<span class="ff3">充</span>分<span class="ff3">．</span> </div><div class="t m0 x1 h4 y5 ff1 fs0 fc0 sc0 ls0 ws0">D. <span class="ff3">相同结<span class="ff2">构电路部分，</span>尽<span class="ff2">可能</span>采<span class="ff2">用</span>“<span class="ff2">对称</span>式”<span class="ff2">标准布局</span>；<span class="ff2"> </span></span></div><div class="t m0 x1 h4 y2b ff1 fs0 fc0 sc0 ls0 ws0">E. <span class="ff2">按照均<span class="ff3">匀</span>分布、<span class="ff3">重心平衡</span>、版<span class="ff3">面美观</span>的标准<span class="ff3">优化</span>布局<span class="ff3">；</span> </span></div><div class="t m0 x1 h4 y7 ff1 fs0 fc0 sc0 ls0 ws0">F. <span class="ff2">器件布局<span class="ff3">栅格</span>的设置，一般<span class="_ _0"> </span></span>IC<span class="_ _0"> </span><span class="ff2">器件布局时，<span class="ff3">栅格</span>应为<span class="_ _0"> </span></span>50--100 mil,<span class="ff3">小型<span class="ff2">表</span>面安<span class="ff2">装器件，</span>如<span class="ff2">表</span>面贴<span class="ff2">装元</span></span></div><div class="t m0 x1 h4 y8 ff2 fs0 fc0 sc0 ls0 ws0">件布局时，<span class="ff3">栅格</span>设置应<span class="ff3">不少</span>于<span class="_ _0"> </span><span class="ff1">25mil</span>。 </div><div class="t m0 x1 h4 y9 ff1 fs0 fc0 sc0 ls0 ws0">G. <span class="ff3">如<span class="ff2">有</span>特殊<span class="ff2">布局要求，应</span>双<span class="ff2">方</span>沟<span class="ff2">通后</span>确<span class="ff2">定。 </span></span></div><div class="t m0 x1 h4 ya ff1 fs0 fc0 sc0 ls0 ws0">5. <span class="ff3">同类型插<span class="ff2">装元器件在<span class="_ _0"> </span></span></span>X<span class="_ _0"> </span><span class="ff2">或<span class="_ _0"> </span></span>Y<span class="_ _0"> </span><span class="ff2">方<span class="ff3">向</span>上应朝一<span class="ff3">个</span>方<span class="ff3">向</span>放置。<span class="ff3">同</span>一种<span class="ff3">类型</span>的有<span class="ff3">极</span>性分<span class="ff3">立</span>元件<span class="ff3">也</span>要<span class="ff3">力争</span>在<span class="_ _0"> </span></span>X<span class="_ _0"> </span><span class="ff2">或</span></div><div class="t m0 x1 h4 yb ff1 fs0 fc0 sc0 ls0 ws0">Y<span class="_ _0"> </span><span class="ff2">方<span class="ff3">向</span>上<span class="ff3">保</span>持一<span class="ff3">致</span>，<span class="ff3">便</span>于生产和<span class="ff3">检验</span>。 </span></div><div class="t m0 x1 h4 yc ff1 fs0 fc0 sc0 ls0 ws0">6. <span class="ff2">发<span class="ff3">热</span>元件要一般应均<span class="ff3">匀</span>分布，以利于单板和整<span class="ff3">机</span>的<span class="ff3">散热</span>，<span class="ff3">除温度检</span>测元件以<span class="ff3">外</span>的<span class="ff3">温度敏感</span>器件应<span class="ff3">远离</span></span></div><div class="t m0 x1 h4 yd ff2 fs0 fc0 sc0 ls0 ws0">发<span class="ff3">热</span>量<span class="ff3">大</span>的元器件。 </div><div class="t m0 x1 h4 ye ff1 fs0 fc0 sc0 ls0 ws0">7. <span class="ff2">元器件的<span class="ff3">排</span>列要<span class="ff3">便</span>于<span class="ff3">调</span>试和维修，<span class="ff3">亦即小</span>元件周围<span class="ff3">不</span>能放置<span class="ff3">大</span>元件、需<span class="ff3">调</span>试的元、器件周围要有<span class="ff3">足够</span></span></div><div class="t m0 x1 h4 y2c ff2 fs0 fc0 sc0 ls0 ws0">的<span class="ff3">空</span>间。 </div><div class="t m0 x1 h4 y2d ff1 fs0 fc0 sc0 ls0 ws0">8. <span class="ff2">需用<span class="ff3">波峰焊</span>工艺生产的单板，其<span class="ff3">紧固</span>件<span class="ff3">安</span>装<span class="ff3">孔</span>和定位<span class="ff3">孔</span>都应为<span class="ff3">非金</span>属<span class="ff3">化孔</span>。当<span class="ff3">安</span>装<span class="ff3">孔</span>需要接<span class="ff3">地</span>时</span>, <span class="ff2">应<span class="ff3">采</span></span></div><div class="t m0 x1 h4 yf ff2 fs0 fc0 sc0 ls0 ws0">用分布接<span class="ff3">地小孔</span>的方<span class="ff3">式与地平面</span>连接。 </div><div class="t m0 x1 h4 y10 ff1 fs0 fc0 sc0 ls0 ws0">9. <span class="ff3">焊<span class="ff2">接</span>面<span class="ff2">的</span>贴<span class="ff2">装元件</span>采<span class="ff2">用</span>波峰焊<span class="ff2">接生产工艺时，</span>阻<span class="ff2">、</span>容<span class="ff2">件</span>轴向<span class="ff2">要</span>与波峰焊传送<span class="ff2">方</span>向垂直<span class="ff2">， </span>阻排及</span></div><div class="t m0 x1 h4 y11 ff1 fs0 fc0 sc0 ls0 ws0">SOP<span class="ff2">（</span>PIN<span class="_ _0"> </span><span class="ff2">间<span class="ff3">距大</span>于等于<span class="_ _0"> </span></span>1.27mm<span class="ff2">）元器件<span class="ff3">轴向与传送</span>方<span class="ff3">向平</span>行<span class="ff3">；</span></span>PIN<span class="_ _0"> </span><span class="ff2">间<span class="ff3">距小</span>于<span class="_ _0"> </span></span>1.27mm<span class="ff2">（</span>50mil)<span class="ff2">的</span></div><div class="t m0 x1 h4 y12 ff1 fs0 fc0 sc0 ls0 ws0">IC<span class="ff2">、</span>SOJ<span class="ff2">、</span>PLCC<span class="ff2">、</span>QFP<span class="_ _0"> </span><span class="ff2">等有<span class="ff3">源</span>元件<span class="ff3">避免</span>用<span class="ff3">波峰焊焊</span>接。 </span></div><div class="t m0 x1 h4 y13 ff1 fs0 fc0 sc0 ls0 ws0">10. BGA<span class="_ _0"> </span><span class="ff3">与相邻<span class="ff2">元件的</span>距离</span>>5mm<span class="ff2">。其<span class="ff3">它贴片</span>元件<span class="ff3">相互</span>间的<span class="ff3">距离</span></span>>0.7mm<span class="ff3">；贴<span class="ff2">装元件</span>焊盘<span class="ff2">的</span>外侧与相邻</span></div><div class="t m0 x1 h4 y14 ff3 fs0 fc0 sc0 ls0 ws0">插<span class="ff2">装元件的</span>外侧距离大<span class="ff2">于<span class="_ _0"> </span><span class="ff1">2mm</span></span>；<span class="ff2">有</span>压<span class="ff2">接件的<span class="_ _0"> </span><span class="ff1">PCB</span>，</span>压<span class="ff2">接的接</span>插<span class="ff2">件周围<span class="_ _0"> </span><span class="ff1">5mm<span class="_ _0"> </span></span></span>内不<span class="ff2">能有</span>插<span class="ff2">装元、器件，在</span></div><div class="t m0 x1 h4 y2e ff3 fs0 fc0 sc0 ls0 ws0">焊<span class="ff2">接</span>面<span class="ff2">其周围<span class="_ _0"> </span><span class="ff1">5mm<span class="_ _0"> </span></span></span>内也不<span class="ff2">能有</span>贴<span class="ff2">装元、器件。 </span></div><div class="t m0 x1 h4 y16 ff1 fs0 fc0 sc0 ls0 ws0">11. IC<span class="_ _0"> </span><span class="ff3">去偶<span class="ff2">电</span>容<span class="ff2">的布局要</span>尽<span class="ff2">量</span>靠近<span class="_ _0"> </span></span>IC<span class="_ _0"> </span><span class="ff2">的电<span class="ff3">源管脚</span>，并使之<span class="ff3">与</span>电<span class="ff3">源</span>和<span class="ff3">地</span>之间<span class="ff3">形</span>成的<span class="ff3">回</span>路最<span class="ff3">短</span>。 </span></div><div class="t m0 x1 h4 y2f ff1 fs0 fc0 sc0 ls0 ws0">12. <span class="ff2">元件布局时</span>,<span class="ff2">应适当<span class="ff3">考虑</span>使用<span class="ff3">同</span>一种电<span class="ff3">源</span>的器件<span class="ff3">尽</span>量放在一起</span>, <span class="ff2">以<span class="ff3">便</span>于<span class="ff3">将来</span>的电<span class="ff3">源</span>分<span class="ff3">隔</span>。 </span></div><div class="t m0 x1 h4 y18 ff1 fs0 fc0 sc0 ls0 ws0">13. <span class="ff2">用于<span class="ff3">阻抗匹配</span>目的<span class="ff3">阻容</span>器件的布局，要根据其属性<span class="ff3">合</span>理布置。 </span></div><div class="t m0 x1 h4 y19 ff3 fs0 fc0 sc0 ls0 ws0">串联匹配<span class="ff2">电</span>阻<span class="ff2">的布局要</span>靠近该<span class="ff2">信号的</span>驱<span class="ff2">动</span>端<span class="ff2">，</span>距离<span class="ff2">一般</span>不超<span class="ff2">过<span class="_ _0"> </span><span class="ff1">500mil</span>。 </span></div><div class="t m0 x1 h4 y1a ff3 fs0 fc0 sc0 ls0 ws0">匹配<span class="ff2">电</span>阻<span class="ff2">、电</span>容<span class="ff2">的布局一定要分</span>清<span class="ff2">信号的</span>源端与终端<span class="ff2">，对于多</span>负载<span class="ff2">的</span>终端匹配<span class="ff2">一定要在信号的最</span>远端匹配<span class="ff2">。</span></div><div class="t m0 x1 h4 y1b ff2 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h4 y1c ff1 fs0 fc0 sc0 ls0 ws0">14. <span class="ff2">布局完成后<span class="ff3">打</span>印出装<span class="ff3">配</span>图供原理图设计者<span class="ff3">检查</span>器件封装的<span class="ff3">正确</span>性，并<span class="ff3">且确认</span>单板、<span class="ff3">背</span>板和接<span class="ff3">插</span>件的信</span></div><div class="t m0 x1 h4 y1d ff2 fs0 fc0 sc0 ls0 ws0">号对应关系，经<span class="ff3">确认无误</span>后方可<span class="ff3">开始</span>布线。 </div><div class="t m0 x1 h4 y1e ff1 fs0 fc0 sc0 ls0 ws0">C. <span class="ff2">设置布线约<span class="ff3">束</span>条件 </span></div><div class="t m0 x1 h4 y1f ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff3">报告<span class="ff2">设计</span>参数<span class="ff2"> </span></span>8 </div><div class="t m0 x1 h4 y20 ff2 fs0 fc0 sc0 ls0 ws0">布局<span class="ff3">基</span>本<span class="ff3">确</span>定后，应用<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span>设计工具的<span class="ff3">统</span>计<span class="ff3">功</span>能，<span class="ff3">报告</span>网络<span class="ff3">数</span>量，网络<span class="ff3">密度</span>，<span class="ff3">平</span>均<span class="ff3">管脚密度</span>等<span class="ff3">基</span>本<span class="ff3">参数</span>，</div><div class="t m0 x1 h4 y30 ff2 fs0 fc0 sc0 ls0 ws0">以<span class="ff3">便确</span>定所需要的信号布线<span class="ff3">层数</span>。 </div><div class="t m0 x1 h4 y21 ff2 fs0 fc0 sc0 ls0 ws0">信号<span class="ff3">层数</span>的<span class="ff3">确</span>定可<span class="ff3">参考</span>以下经<span class="ff3">验数</span>据 </div><div class="t m0 x1 h4 y22 ff1 fs0 fc0 sc0 ls0 ws0">Pin<span class="_ _0"> </span><span class="ff3">密度<span class="ff2"> </span></span></div><div class="t m0 x1 h4 y23 ff2 fs0 fc0 sc0 ls0 ws0">信号<span class="ff3">层数</span> </div><div class="t m0 x1 h4 y24 ff2 fs0 fc0 sc0 ls0 ws0">板<span class="ff3">层数</span> </div></div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62677ce64f8811599eed1451/bg4.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h4 y2c ff3 fs0 fc0 sc0 ls0 ws0">注<span class="ff2">：<span class="ff1">PIN<span class="_ _0"> </span></span></span>密度<span class="ff2">的定义为： 板</span>面积<span class="ff2">（</span>平<span class="ff2">方</span>英寸<span class="ff2">）<span class="ff1">/</span>（板上</span>管脚总数<span class="ff1">/14<span class="ff2">） </span></span></div><div class="t m0 x1 h4 y2d ff2 fs0 fc0 sc0 ls0 ws0">布线<span class="ff3">层数</span>的具<span class="ff3">体确</span>定<span class="ff3">还</span>要<span class="ff3">考虑</span>单板的可<span class="ff3">靠</span>性要求，信号的工<span class="ff3">作速度</span>，制<span class="ff3">造</span>成本和<span class="ff3">交货期</span>等<span class="ff3">因素</span>。 </div><div class="t m0 x1 h4 yf ff1 fs0 fc0 sc0 ls0 ws0">1. <span class="ff2">布线<span class="ff3">层</span>设置 </span></div><div class="t m0 x1 h4 y10 ff2 fs0 fc0 sc0 ls0 ws0">在高<span class="ff3">速数字</span>电路设计中，电<span class="ff3">源与地层</span>应<span class="ff3">尽</span>量<span class="ff3">靠</span>在一起，中间<span class="ff3">不安排</span>布线。所有布线<span class="ff3">层</span>都<span class="ff3">尽</span>量<span class="ff3">靠近</span>一<span class="ff3">平面层</span>，</div><div class="t m0 x1 h4 y11 ff3 fs0 fc0 sc0 ls0 ws0">优选地平面<span class="ff2">为</span>走<span class="ff2">线</span>隔离层<span class="ff2">。 </span></div><div class="t m0 x1 h4 y12 ff2 fs0 fc0 sc0 ls0 ws0">为了<span class="ff3">减少层</span>间信号的电<span class="ff3">磁干扰</span>，<span class="ff3">相邻</span>布线<span class="ff3">层</span>的信号线<span class="ff3">走向</span>应<span class="ff3">取垂直</span>方<span class="ff3">向</span>。 </div><div class="t m0 x1 h4 y13 ff2 fs0 fc0 sc0 ls0 ws0">可以根据需要设计<span class="_ _0"> </span><span class="ff1">1--2<span class="_ _0"> </span><span class="ff3">个阻抗控</span></span>制<span class="ff3">层</span>，<span class="ff3">如</span>果需要<span class="ff3">更</span>多的<span class="ff3">阻抗控</span>制<span class="ff3">层</span>需要<span class="ff3">与<span class="_ _0"> </span><span class="ff1">PCB<span class="_ _0"> </span></span></span>产家<span class="ff3">协商</span>。<span class="ff3">阻抗控</span>制<span class="ff3">层</span>要</div><div class="t m0 x1 h4 y14 ff2 fs0 fc0 sc0 ls0 ws0">按要求标<span class="ff3">注清楚</span>。<span class="ff3">将</span>单板上有<span class="ff3">阻抗控</span>制要求的网络布线分布在<span class="ff3">阻抗控</span>制<span class="ff3">层</span>上。 </div><div class="t m0 x1 h4 y2e ff1 fs0 fc0 sc0 ls0 ws0">2. <span class="ff2">线<span class="ff3">宽</span>和线间<span class="ff3">距</span>的设置 </span></div><div class="t m0 x1 h4 y16 ff2 fs0 fc0 sc0 ls0 ws0">线<span class="ff3">宽</span>和线间<span class="ff3">距</span>的设置要<span class="ff3">考虑</span>的<span class="ff3">因素</span> </div><div class="t m0 x1 h4 y2f ff1 fs0 fc0 sc0 ls0 ws0">A. <span class="ff2">单板的<span class="ff3">密度</span>。板的<span class="ff3">密度越</span>高，<span class="ff4">倾<span class="ff3">向</span></span>于使用<span class="ff3">更细</span>的线<span class="ff3">宽</span>和<span class="ff3">更<span class="ff4">窄</span></span>的间<span class="ff4">隙</span>。 </span></div><div class="t m0 x1 h4 y18 ff1 fs0 fc0 sc0 ls0 ws0">B. <span class="ff2">信号的电流<span class="ff4">强<span class="ff3">度</span></span>。当信号的<span class="ff3">平</span>均电流<span class="ff4">较<span class="ff3">大</span></span>时，应<span class="ff3">考虑</span>布线<span class="ff3">宽度</span>所能<span class="ff4">承<span class="ff3">载</span></span>的的电流，线<span class="ff3">宽</span>可<span class="ff3">参考</span>以下<span class="ff3">数</span></span></div><div class="t m0 x1 h4 y19 ff2 fs0 fc0 sc0 ls0 ws0">据： </div><div class="t m0 x1 h4 y1a ff1 fs0 fc0 sc0 ls0 ws0">PCB<span class="_ _0"> </span><span class="ff2">设计时<span class="ff4">铜箔厚<span class="ff3">度</span></span></span>,<span class="ff3">走<span class="ff2">线</span>宽度<span class="ff2">和电流的关系 </span></span></div><div class="t m0 x1 h4 y1b ff3 fs0 fc0 sc0 ls0 ws0">不同<span class="ff4">厚</span>度<span class="ff2">，</span>不同宽度<span class="ff2">的<span class="ff4">铜箔</span>的</span>载<span class="ff2">流量<span class="ff4">见</span>下表<span class="ff1">: </span></span></div><div class="t m0 x1 h4 y1c ff4 fs0 fc0 sc0 ls0 ws0">铜皮厚<span class="ff3">度<span class="_ _0"> </span><span class="ff1">35um </span></span>铜皮厚<span class="ff3">度<span class="_ _0"> </span><span class="ff1">50um </span></span>铜皮厚<span class="ff3">度<span class="_ _0"> </span><span class="ff1">70um </span></span></div><div class="t m0 x1 h4 y1d ff4 fs0 fc0 sc0 ls0 ws0">铜皮<span class="_ _0"> </span><span class="ff1">Δt=10℃<span class="ff5"> </span></span>铜皮<span class="_ _0"> </span><span class="ff1">Δt=10℃<span class="ff5"> </span></span>铜皮<span class="_ _0"> </span><span class="ff1">Δt=10℃<span class="ff5"> </span></span></div></div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
