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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625bcfbd92dc900e62302c13/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">OMAP5910<span class="_ _0"></span> Dual-Core<span class="_ _0"></span> Processor</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">Clock<span class="_ _0"></span> Generation<span class="_ _0"></span> and<span class="_ _0"></span> System<span class="_ _0"></span> Reset<span class="_ _0"></span> Management</div><div class="t m0 x3 h2 y3 ff1 fs0 fc0 sc0 ls1 ws2">Reference<span class="_ _0"></span> Guide</div><div class="t m0 x4 h3 y4 ff2 fs1 fc0 sc0 ls2 ws3">Literature Number: SPRU678A</div><div class="t m0 x5 h3 y5 ff2 fs1 fc0 sc0 ls3 ws4">October 2003 − Revised July 2005</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625bcfbd92dc900e62302c13/bg2.jpg"><div class="t m0 x6 h4 y6 ff3 fs2 fc0 sc0 ls4 ws5">IMPORT<span class="_ _1"></span>ANT NOTICE</div><div class="t m0 x7 h5 y7 ff2 fs2 fc0 sc0 ls4 ws6">T<span class="_ _2"></span>exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,</div><div class="t m0 x7 h5 y8 ff2 fs2 fc0 sc0 ls5 ws7">modifications, enhancements, improvements, and other changes to its products and services at any</div><div class="t m0 x7 h5 y9 ff2 fs2 fc0 sc0 ls4 ws8">time and to discontinue any product or service without notice. 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Use of such information may require a license from</span></div><div class="t m0 x7 h5 y1a ff2 fs2 fc0 sc0 ls13 ws4">a third party under the patents or other intellectual property of <span class="ls14 wsb">the third party<span class="_ _1"></span>, or a license from TI under</span></div><div class="t m0 x7 h5 y1b ff2 fs2 fc0 sc0 ls15 ws4">the patents or other intellectual property of TI.</div><div class="t m0 x7 h5 y1c ff2 fs2 fc0 sc0 ls4 ws13">Reproduction o<span class="_ _1"></span>f <span class="ls16 ws4">information in TI data books or data sheets <span class="ls17">is permissible only if reproduction is without</span></span></div><div class="t m0 x7 h5 y1d ff2 fs2 fc0 sc0 ls4 ws14">alteration and is accompanied by all associated warranties, conditions, limitations, and notices.</div><div class="t m0 x7 h5 y1e ff2 fs2 fc0 sc0 ls5 ws15">Reproduction of <span class="ls18 ws4">this information with alteration is an unfair and deceptive business practice. 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TI is not responsible or liable for any such</span></div><div class="t m0 x7 h5 y23 ff2 fs2 fc0 sc0 ls4 ws4">statements.</div><div class="t m0 x7 h5 y24 ff2 fs2 fc0 sc0 ls4 ws1a">Following are URLs where you can obtain information on other T<span class="_ _4"></span>exas Instruments products and</div><div class="t m0 x7 h5 y25 ff2 fs2 fc0 sc0 ls15 wsb">application solutions:</div><div class="t m0 x8 h6 y26 ff3 fs3 fc0 sc0 ls4 ws4">Products<span class="_ _6"> </span>Applications</div><div class="t m0 x8 h7 y27 ff2 fs3 fc0 sc0 ls4 ws4">Amplifiers<span class="_ _7"> </span>amplifier<span class="_ _1"></span>.ti.com<span class="_ _8"> </span>Audio<span class="_ _9"> </span>www<span class="_ _1"></span>.ti.com/audio</div><div class="t m0 x8 h7 y28 ff2 fs3 fc0 sc0 ls1f ws1b">Data Converters<span class="_ _a"> </span>dataconverter<span class="_ _1"></span>.ti.com<span class="_ _b"> </span>Automotive<span class="_ _c"> </span>www<span class="_ _1"></span>.ti.com/automotive</div><div class="t m0 x8 h7 y29 ff2 fs3 fc0 sc0 ls4 ws4">DSP<span class="_ _d"> </span>dsp.ti.com<span class="_ _e"> </span>Broadband<span class="_ _f"> </span>www<span class="_ _1"></span>.ti.com/broadband</div><div class="t m0 x8 h7 y2a ff2 fs3 fc0 sc0 ls20 ws1c">Interface<span class="_ _10"> </span>interface.ti.com<span class="_ _11"> </span>Digital Control<span class="_ _12"> </span>www<span class="_ _1"></span>.ti.com/digitalcontrol</div><div class="t m0 x8 h7 y2b ff2 fs3 fc0 sc0 ls4 ws4">Logic<span class="_ _13"> </span>logic.ti.com<span class="_ _14"> </span>Military<span class="_ _15"> </span>www<span class="_ _1"></span>.ti.com/military</div><div class="t m0 x8 h7 y2c ff2 fs3 fc0 sc0 ls21 ws1d">Power Mgmt<span class="_ _16"> </span>power<span class="_ _1"></span>.ti.com<span class="_ _17"> </span>Optical Networking<span class="_ _18"> </span>www<span class="_ _1"></span>.ti.com/opticalnetwork</div><div class="t m0 x8 h7 y2d ff2 fs3 fc0 sc0 ls4 ws4">Microcontrollers<span class="_ _19"> </span>microcontroller<span class="_ _1"></span>.ti.com<span class="_ _1a"> </span>Security<span class="_ _1b"> </span>www<span class="_ _1"></span>.ti.com/security</div><div class="t m0 x9 h7 y2e ff2 fs3 fc0 sc0 ls4 ws4">T<span class="_ _2"></span>elephony<span class="_ _11"> </span>www<span class="_ _1"></span>.ti.com/telephony</div><div class="t m0 x9 h7 y2f ff2 fs3 fc0 sc0 ls22 ws1e">Video & Imaging<span class="_ _1c"> </span>www<span class="_ _1"></span>.ti.com/video</div><div class="t m0 x9 h7 y30 ff2 fs3 fc0 sc0 ls4 ws4">Wireless<span class="_ _1d"> </span>www<span class="_ _1"></span>.ti.com/wireless</div><div class="t m0 x8 h7 y31 ff2 fs3 fc0 sc0 ls23 ws4">Mailing Address:<span class="_ _1e"> </span>T<span class="_ _2"></span>exas Instruments</div><div class="t m0 xa h7 y32 ff2 fs3 fc0 sc0 ls24 ws1f">Post Office Box 655303 Dallas, T<span class="_ _4"></span>exas 75265</div><div class="t m0 xb h3 y33 ff2 fs1 fc0 sc0 ls25 ws4">Copyright <span class="ff4 ls4"></span><span class="ls26 ws20"> 2005, T<span class="_ _4"></span>exas Instruments Incorporated</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625bcfbd92dc900e62302c13/bg3.jpg"><div class="t m0 xc h3 y34 ff2 fs1 fc0 sc0 ls4 ws4">5</div><div class="t m0 xd h8 y35 ff5 fs1 fc0 sc0 ls27 ws4">OMAP5910<span class="_ _1f"></span><span class="ls4">SPRU678A</span></div><div class="t m0 xe h9 y36 ff3 fs4 fc0 sc0 ls4 ws4">Preface</div><div class="t m0 xf ha y37 ff6 fs5 fc0 sc0 ls4 ws4">Read This First</div><div class="t m0 x10 hb y38 ff1 fs6 fc0 sc0 ls4 ws21">About This Manual</div><div class="t m0 x11 hc y39 ff2 fs7 fc0 sc0 ls4 ws22">This document describes clock generation and system reset for the</div><div class="t m0 x11 hc y3a ff2 fs7 fc0 sc0 ls28 ws23">OMAP5910 multimedia processor<span class="_ _1"></span>.</div><div class="t m0 x10 hb y3b ff1 fs6 fc0 sc0 ls4 ws24">Notational Conventions</div><div class="t m0 x11 hc y3c ff2 fs7 fc0 sc0 ls29 ws4">This document uses the following conventions.</div><div class="t m0 x11 hc y3d ff7 fs1 fc0 sc0 ls4 ws4">-<span class="_ _20"> </span><span class="ff2 fs7 ws25">Hexadecimal numbers are shown with the suffix h. For example, the</span></div><div class="t m0 x12 hc y3e ff2 fs7 fc0 sc0 ls28 ws23">following number is 40 hexadecimal (decimal 64): 40h.</div><div class="t m0 x10 hb y3f ff1 fs6 fc0 sc0 ls4 ws21">Related Documentation From T<span class="_ _1"></span>exas Instruments</div><div class="t m0 x11 hc y40 ff2 fs7 fc0 sc0 ls4 ws26">The following documents describe the OMAP5910 device and related</div><div class="t m0 x11 hc y41 ff2 fs7 fc0 sc0 ls4 ws27">peripherals. Copies of these documents are available on the Internet at</div><div class="t m0 x11 hd y42 ff2 fs7 fc0 sc0 ls2a ws4">www<span class="_ _1"></span>.ti.com. <span class="_ _21"></span><span class="ff5 ls4">Tip:<span class="ff2 ws28"> Enter the literature number in the search box provided at</span></span></div><div class="t m0 x11 hc y43 ff2 fs7 fc0 sc0 ls4 ws4">www<span class="_ _1"></span>.ti.com.</div><div class="t m0 x11 he y44 ff1 fs7 fc0 sc0 ls2b ws29">OMAP5910 Dual-Core Processor M<span class="_ _3"></span>PU Subsystem Reference Guide<span class="ff2 ls2c ws4"> (litera-</span></div><div class="t m0 x11 hc y45 ff2 fs7 fc0 sc0 ls29 ws2a">ture number SPRU671)</div><div class="t m0 x11 he y46 ff1 fs7 fc0 sc0 ls2d ws2b">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> DSP<span class="_ _5"></span> Subsystem<span class="_ _5"></span> Reference Guide</div><div class="t m0 x11 hc y47 ff2 fs7 fc0 sc0 ls2e ws2c">(literature number SPRU672)</div><div class="t m0 x11 he y48 ff1 fs7 fc0 sc0 ls2f ws2d">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Memory<span class="_ _5"></span><span class="ls30 ws2e"> Interface<span class="_ _5"></span> Traffic Controller</span></div><div class="t m0 x11 he y49 ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU673)</span></div><div class="t m0 x11 he y4a ff1 fs7 fc0 sc0 ls2d ws30">OMAP5910 D<span class="_ _3"></span>ual-Core Pr<span class="_ _3"></span>ocessor S<span class="_ _3"></span>ystem D<span class="_ _3"></span>MA C<span class="_ _3"></span>ontroller <span class="_ _0"></span><span class="ls31 ws4">Reference Guide</span></div><div class="t m0 x11 hc y4b ff2 fs7 fc0 sc0 ls2e ws2c">(literature number SPRU674)</div><div class="t m0 x11 he y4c ff1 fs7 fc0 sc0 ls32 ws31">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> LCD<span class="_ _5"></span> Controller<span class="_ _5"></span> <span class="ls4 ws32">Reference Guide<span class="ff2 ws33"> (litera-</span></span></div><div class="t m0 x11 hc y4d ff2 fs7 fc0 sc0 ls29 ws2a">ture number SPRU675)</div><div class="t m0 x11 he y4e ff1 fs7 fc0 sc0 ls33 ws34">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> <span class="ls4 ws35">Universal Asynchronous</span></div><div class="t m0 x11 he y4f ff1 fs7 fc0 sc0 ls2e ws36">Receiver/Transmitter (<span class="_ _2"></span>UAR<span class="_ _1"></span>T<span class="_ _3"></span>) <span class="ls2c ws37">D<span class="_ _1"></span>evi<span class="_ _1"></span>ces Reference Guide<span class="ff2 ls34 ws4"> (literature number</span></span></div><div class="t m0 x11 hc y50 ff2 fs7 fc0 sc0 ls4 ws4">SPRU676)</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625bcfbd92dc900e62302c13/bg4.jpg"><div class="t m0 x13 h8 y51 ff5 fs1 fc0 sc0 ls4 ws4"><span class="fc1 sc0">T</span><span class="_ _1"></span><span class="fc1 sc0">rademarks</span></div><div class="t m0 x13 h3 y52 ff2 fs1 fc0 sc0 ls4 ws4">6</div><div class="t m0 x14 h8 y53 ff5 fs1 fc0 sc0 ls4 ws4"> <span class="_ _22"></span><span class="ls27">OMAP5910<span class="_ _23"> </span><span class="ls4">SPRU678A</span></span></div><div class="t m0 x15 he y54 ff1 fs7 fc0 sc0 ls35 ws38">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Universal<span class="_ _5"></span> Serial<span class="_ _5"></span> Bus (USB)<span class="_ _5"></span> <span class="ls4 ws39">and Fr<span class="_ _3"></span>am<span class="_ _1"></span>e</span></div><div class="t m0 x15 he y55 ff1 fs7 fc0 sc0 ls36 ws3a">Adjustment Counter<span class="_ _5"></span> (F<span class="_ _1"></span>AC)<span class="_ _5"></span> <span class="ls24 ws4">Reference Guide<span class="ff2 ls37"> (literature number SPRU677)</span></span></div><div class="t m0 x15 he y56 ff1 fs7 fc0 sc0 ls38 ws3b">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Clock<span class="_ _5"></span> Generation<span class="_ _5"></span> and<span class="_ _5"></span> System Reset</div><div class="t m0 x15 he y57 ff1 fs7 fc0 sc0 ls2a ws4">Ma<span class="_ _1"></span>na<span class="_ _3"></span>ge<span class="_ _1"></span>me<span class="_ _1"></span>nt Reference Guide<span class="ff2"> (literature number SPRU678)</span></div><div class="t m0 x15 he y58 ff1 fs7 fc0 sc0 ls32 ws3c">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Gene<span class="ls36 ws3d">ral-Purpose<span class="_ _5"></span> Input/Output<span class="_ _5"></span> (GPIO)</span></div><div class="t m0 x15 he y59 ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU679)</span></div><div class="t m0 x15 he y5a ff1 fs7 fc0 sc0 ls39 ws3e">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> MMC/SD<span class="_ _5"></span> <span class="ls4 ws3f">Reference Guide<span class="ff2 ws40"> (literature</span></span></div><div class="t m0 x15 hc y5b ff2 fs7 fc0 sc0 ls3a ws41">number SPRU680)</div><div class="t m0 x15 he y5c ff1 fs7 fc0 sc0 ls32 ws42">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Inter-In<span class="ls38 ws43">tegrated<span class="_ _5"></span> Circuit<span class="_ _5"></span> (I2C)<span class="_ _5"></span> Controller</span></div><div class="t m0 x15 he y5d ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU681)</span></div><div class="t m0 x15 he y5e ff1 fs7 fc0 sc0 ls3b ws44">OMAP5910<span class="_ _5"></span> D<span class="_ _5"></span>ua<span class="_ _5"></span>l<span class="_ _5"></span>-C<span class="_ _5"></span>o<span class="_ _5"></span>re<span class="_ _0"></span> Pro<span class="_ _5"></span><span class="ls36 ws45">cessor<span class="_ _5"></span> T<span class="_ _1"></span>ime<span class="_ _1"></span>r<span class="_ _5"></span> Ref<span class="_ _1"></span>ere<span class="_ _3"></span>nc<span class="_ _1"></span>e<span class="_ _5"></span> Gui<span class="_ _1"></span>de<span class="_ _5"></span><span class="ff2 ls2a ws4"> (literature number</span></span></div><div class="t m0 x15 hc y5f ff2 fs7 fc0 sc0 ls4 ws4">SPRU682)</div><div class="t m0 x15 he y60 ff1 fs7 fc0 sc0 ls32 ws46">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Inter-Processor<span class="_ _5"></span> Communication</div><div class="t m0 x15 he y61 ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU683)</span></div><div class="t m0 x15 he y62 ff1 fs7 fc0 sc0 ls39 ws47">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Camera<span class="_ _5"></span> Interface<span class="_ _5"></span> <span class="ls4 ws48">Reference Guide</span></div><div class="t m0 x15 hc y63 ff2 fs7 fc0 sc0 ls2e ws2c">(literature number SPRU684)</div><div class="t m0 x15 he y64 ff1 fs7 fc0 sc0 ls33 ws49">OMAP5905 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> <span class="ls4 ws4a">Multichannel Serial Interface (MCSI)</span></div><div class="t m0 x15 he y65 ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU685)</span></div><div class="t m0 x15 he y66 ff1 fs7 fc0 sc0 ls33 ws4b">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> Micro-Wire Interface<span class="_ _5"></span> <span class="ls4 ws4c">Reference Guide</span></div><div class="t m0 x15 hc y67 ff2 fs7 fc0 sc0 ls2e ws2c">(literature number SPRU686)</div><div class="t m0 x15 he y68 ff1 fs7 fc0 sc0 ls32 ws4d">OMAP5910 Dual-Core Processor Real-Time Clock (R<span class="_ _3"></span>TC) <span class="_ _5"></span><span class="ls3c ws4e">Reference Guide</span></div><div class="t m0 x15 hc y69 ff2 fs7 fc0 sc0 ls2e ws2c">(literature number SPRU687)</div><div class="t m0 x15 he y6a ff1 fs7 fc0 sc0 ls35 ws4f">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> HDQ/1-Wire Interface<span class="_ _5"></span> <span class="_ _5"></span><span class="ls4 ws50">Reference Guide</span></div><div class="t m0 x15 hc y6b ff2 fs7 fc0 sc0 ls2e ws2c">(literature number SPRU688)</div><div class="t m0 x15 he y6c ff1 fs7 fc0 sc0 ls33 ws51">OMAP5910 Dual-Core<span class="_ _5"></span> Processor<span class="_ _5"></span> PW<span class="ws52">L,<span class="_ _5"></span> PWT<span class="_ _1"></span>, and<span class="_ _5"></span> LED<span class="_ _5"></span> Peripheral</span></div><div class="t m0 x15 he y6d ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU689)</span></div><div class="t m0 x15 he y6e ff1 fs7 fc0 sc0 ls3d ws53">OMAP5910 D<span class="_ _3"></span>ual-Core Processor M<span class="_ _1"></span>ul<span class="_ _1"></span>tic<span class="_ _3"></span>ha<span class="_ _3"></span>nne<span class="_ _1"></span>l Bu<span class="_ _1"></span>ff<span class="_ _3"></span>er<span class="_ _3"></span>ed S<span class="_ _1"></span>er<span class="_ _1"></span>ial P<span class="_ _1"></span>or<span class="_ _1"></span>t (M<span class="_ _1"></span>cBS<span class="_ _3"></span>P)</div><div class="t m0 x15 he y6f ff1 fs7 fc0 sc0 ls2a ws2f">Reference Guide<span class="ff2 ws4"> (literature number SPRU708)</span></div><div class="t m0 x16 hb y70 ff1 fs6 fc0 sc0 ls4 ws4">Trademarks</div><div class="t m0 x15 hc y71 ff2 fs7 fc0 sc0 ls29 ws54">OMAP and the OMAP symbol are trademarks of T<span class="_ _4"></span>exas Instruments.</div><div class="t m0 x16 h8 y72 ff5 fs1 fc0 sc0 ls3e ws55">Related Documentation From T<span class="_ _2"></span>exas Instruments<span class="_"> </span>/<span class="_"> </span>T<span class="_ _1"></span>rademarks</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625bcfbd92dc900e62302c13/bg5.jpg"><div class="t m0 x17 h8 y73 ff5 fs1 fc0 sc0 ls4 ws4"><span class="fc1 sc0">Contents</span></div><div class="t m0 xc h3 y74 ff2 fs1 fc0 sc0 ls4 ws4">7</div><div class="t m0 x18 ha y75 ff6 fs5 fc0 sc0 ls4 ws4">Contents</div><div class="t m0 x10 hf y76 ff3 fs7 fc0 sc0 ls4 ws4">1<span class="_ _24"> </span>Introduction<span class="_ _25"> </span>13<span class="_ _26"></span><span class="ls3f ws54">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="ws4"> . . . . . . </span></span></div><div class="t m0 x19 hc y77 ff2 fs7 fc0 sc0 ls2e ws23">1.1<span class="_ _27"> </span>Clock Generation and System Reset Control<span class="_ _28"> </span>13<span class="_ _29"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y78 ff2 fs7 fc0 sc0 ls41 ws2a">1.1.1<span class="_ _a"> </span>ULPD Module<span class="_ _2a"> </span>17<span class="_ _2b"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y79 ff2 fs7 fc0 sc0 ls2a ws4">1.1.2<span class="_ _a"> </span>Reset Module<span class="_ _2c"> </span>17<span class="_ _2b"></span><span class="ls3f">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y7a ff2 fs7 fc0 sc0 ls41 ws2a">1.1.3<span class="_ _a"> </span>Clock-Generation and Management Module<span class="_ _2d"> </span>18<span class="_ _2e"></span><span class="ls42 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y7b ff2 fs7 fc0 sc0 ls28 ws2c">1.1.4<span class="_ _a"> </span>Memory-Mapped Registers<span class="_ _2f"> </span>19<span class="_ _30"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y7c ff2 fs7 fc0 sc0 ls28 ws56">1.1.5<span class="_ _a"> </span>Clock Domains<span class="_ _31"> </span>19<span class="_ _32"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x10 hf y7d ff3 fs7 fc0 sc0 ls28 ws54">2<span class="_ _24"> </span>Clock Generation<span class="_ _33"> </span><span class="ls4 ws4">20<span class="_ _34"></span><span class="ls3f">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></span></div><div class="t m0 x19 hc y7e ff2 fs7 fc0 sc0 ls2a ws57">2.1<span class="_ _27"> </span>Clocking Schemes<span class="_ _35"> </span>20<span class="_ _36"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y7f ff2 fs7 fc0 sc0 ls2a ws23">2.2<span class="_ _27"> </span>Operating Modes<span class="_ _37"> </span>21<span class="_ _38"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y80 ff2 fs7 fc0 sc0 ls28 ws4">2.3<span class="_ _27"> </span>External-Master Mode<span class="_ _39"> </span>23<span class="_ _2b"></span><span class="ls3f">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y81 ff2 fs7 fc0 sc0 ls4 ws4">2.4<span class="_ _27"> </span>CLKM1<span class="_ _3a"> </span>24<span class="_ _3b"></span><span class="ls43 ws54">. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="ws4"> . . . . . </span></span></div><div class="t m0 x19 hc y82 ff2 fs7 fc0 sc0 ls4 ws4">2.5<span class="_ _27"> </span>CLKM2<span class="_ _3a"> </span>25<span class="_ _3b"></span><span class="ls43 ws54">. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="ws4"> . . . . . </span></span></div><div class="t m0 x19 hc y83 ff2 fs7 fc0 sc0 ls4 ws4">2.6<span class="_ _27"> </span>CLKM3<span class="_ _3a"> </span>28<span class="_ _3b"></span><span class="ls43 ws54">. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="ws4"> . . . . . </span></span></div><div class="t m0 x19 hc y84 ff2 fs7 fc0 sc0 ls29 ws23">2.7<span class="_ _27"> </span>Clock Distribution and Synchronization<span class="_ _3c"> </span>30<span class="_ _3d"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y85 ff2 fs7 fc0 sc0 ls41 ws23">2.8<span class="_ _27"> </span>Low-Power Mode<span class="_ _3e"> </span>31<span class="_ _38"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x10 hf y86 ff3 fs7 fc0 sc0 ls41 ws4">3<span class="_ _24"> </span>Power Management<span class="_ _3f"> </span>32<span class="_ _40"></span><span class="ls3f">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y87 ff2 fs7 fc0 sc0 ls41 ws2c">3.1<span class="_ _27"> </span>DSP-Idle Modes<span class="_ _41"> </span>35<span class="_ _42"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y88 ff2 fs7 fc0 sc0 ls44 ws57">3.1.1<span class="_ _a"> </span>Putting the DSP in IDLE<span class="_ _43"> </span>36<span class="_ _44"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y89 ff2 fs7 fc0 sc0 ls41 ws2c">3.2<span class="_ _27"> </span>MPU-Idle Modes<span class="_ _45"> </span>37<span class="_ _38"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y8a ff2 fs7 fc0 sc0 ls2e ws4">3.2.1<span class="_ _a"> </span>MPU Subdomain (MPU + MPU Interrupt Handler)<span class="_ _46"> </span>37<span class="_ _47"></span><span class="ls45">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y8b ff2 fs7 fc0 sc0 ls2a ws56">3.2.2<span class="_ _a"> </span>DPLL Subdomain<span class="_ _48"> </span>41<span class="_ _49"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y8c ff2 fs7 fc0 sc0 ls2e ws2c">3.2.3<span class="_ _a"> </span>Peripheral Subdomain<span class="_ _4a"> </span>42<span class="_ _4b"></span><span class="ls40 ws54">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y8d ff2 fs7 fc0 sc0 ls28 ws2a">3.3<span class="_ _27"> </span>T<span class="_ _1"></span>raffic-Controller-Idle Modes<span class="_ _4c"> </span>42<span class="_ _4d"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y8e ff2 fs7 fc0 sc0 ls28 ws2a">3.3.1<span class="_ _a"> </span>DPLL-Idle Procedure<span class="_ _4e"> </span>43<span class="_ _4d"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y8f ff2 fs7 fc0 sc0 ls29 ws4">3.4<span class="_ _27"> </span>Chip Idle and W<span class="_ _1"></span>ake-Up Control<span class="_ _4f"> </span>44<span class="_ _4b"></span><span class="ls40 ws54">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y90 ff2 fs7 fc0 sc0 ls28 ws4">3.4.1<span class="_ _a"> </span>Chip-Idle Mode<span class="_ _50"> </span>46<span class="_ _32"></span><span class="ls3f">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y91 ff2 fs7 fc0 sc0 ls2a ws23">3.4.2<span class="_ _a"> </span>Chip-Idle Procedure<span class="_ _51"> </span>46<span class="_ _4d"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y92 ff2 fs7 fc0 sc0 ls2a ws23">3.4.3<span class="_ _a"> </span>W<span class="_ _1"></span>ake-Up Procedure<span class="_ _52"> </span>47<span class="_ _4d"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y93 ff2 fs7 fc0 sc0 ls2a ws56">3.5<span class="_ _27"> </span>Power-Saving Capability<span class="_ _53"> </span>50<span class="_ _54"></span><span class="ls3f ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x19 hc y94 ff2 fs7 fc0 sc0 ls2e ws23">3.6<span class="_ _27"> </span>ULPD Power-Management State Machine<span class="_ _55"> </span>51<span class="_ _56"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y95 ff2 fs7 fc0 sc0 ls2e ws23">3.6.1<span class="_ _a"> </span>Gauging the 32-kHz Oscillator<span class="_ _57"> </span>51<span class="_ _58"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y96 ff2 fs7 fc0 sc0 ls2e ws2c">3.6.2<span class="_ _a"> </span>Gauging V<span class="_ _1"></span>ersus the High-Frequency Clock<span class="_ _59"> </span>51<span class="_ _5a"></span><span class="ls42 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><div class="t m0 x1a hc y97 ff2 fs7 fc0 sc0 ls2e ws23">3.6.3<span class="_ _a"> </span>Control of the 32-kHz Oscillator<span class="_ _5b"> </span>53<span class="_ _5c"></span><span class="ls40 ws4">.<span class="_ _5"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . </span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a 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