CPU_Detect.zip

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  • 2009-11-23 23:17
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this will help to detech the type of cpu
CPU_Detect.zip
  • CPU_Detect
  • cccpudetect
  • cccpudetect.vcproj.VONE.rehan.user
    1.4KB
  • cccpudetect.dll
    8.5KB
  • cccpudetect.suo
    9KB
  • cccpudetect.ncb
    6.3MB
  • cccpudetect.sln
    886B
  • cccpudetect.cpp
    16.6KB
  • cccpudetect.vcproj
    4KB
内容介绍
// Copyright (c) 2005 Intel Corporation // All Rights Reserved // // CPUCount.cpp : Detects three forms of hardware multi-threading support across IA-32 platform // The three forms of HW multithreading are: Multi-processor, Multi-core, and // HyperThreading Technology. // This application enumerates all the logical processors enabled by OS and BIOS, // determine the HW topology of these enabled logical processors in the system // using information provided by CPUID instruction. // A multi-processing system can support any combination of the three forms of HW // multi-threading support. The relevant topology can be identified using a // three level decomposition of the "initial APIC ID" into // Package_id, core_id, and SMT_id. Such decomposition provides a three-level map of // the topology of hardware resources and // allow multi-threaded software to manage shared hardware resources in // the platform to reduce resource contention // Multicore detection algorithm for processor and cache topology requires // all leaf functions of CPUID instructions be available. System administrator // must ensure BIOS settings is not configured to restrict CPUID functionalities. //------------------------------------------------------------------------------------------------- #define HWD_MT_BIT 0x10000000 // EDX[28] Bit 28 is set if HT or multi-core is supported #define NUM_LOGICAL_BITS 0x00FF0000 // EBX[23:16] Bit 16-23 in ebx contains the number of logical // processors per physical processor when execute cpuid with // eax set to 1 #define NUM_CORE_BITS 0xFC000000 // EAX[31:26] Bit 26-31 in eax contains the number of cores minus one // per physical processor when execute cpuid with // eax set to 4. #define INITIAL_APIC_ID_BITS 0xFF000000 // EBX[31:24] Bits 24-31 (8 bits) return the 8-bit unique // initial APIC ID for the processor this code is running on. // Status Flag #define SINGLE_CORE_AND_HT_ENABLED 1 #define SINGLE_CORE_AND_HT_DISABLED 2 #define SINGLE_CORE_AND_HT_NOT_CAPABLE 4 #define MULTI_CORE_AND_HT_NOT_CAPABLE 5 #define MULTI_CORE_AND_HT_ENABLED 6 #define MULTI_CORE_AND_HT_DISABLED 7 #define USER_CONFIG_ISSUE 8 extern "C" { __declspec(dllexport) unsigned int CpuIDSupported(void); __declspec(dllexport) unsigned int GenuineIntel(void); __declspec(dllexport) unsigned int HWD_MTSupported(void); __declspec(dllexport) unsigned int MaxLogicalProcPerPhysicalProc(void); __declspec(dllexport) unsigned int MaxCorePerPhysicalProc(void); __declspec(dllexport) unsigned int find_maskwidth(unsigned int); __declspec(dllexport) unsigned char GetAPIC_ID(void); __declspec(dllexport) unsigned char GetNzbSubID(unsigned char, unsigned char, unsigned char); __declspec(dllexport) unsigned char CPUCount(unsigned int *, unsigned int *, unsigned int *); } unsigned char CPUCount(unsigned int *, unsigned int *, unsigned int *); // Define constant �LINUX� to compile under Linux #ifdef LINUX // The Linux source code listing can be compiled using Linux kernel verison 2.6 // or higher (e.g. RH 4AS-2.8 using GCC 3.4.4). // Due to syntax variances of Linux affinity APIs with earlier kernel versions // and dependence on glibc library versions, compilation on Linux environment // with older kernels and compilers may require kernel patches or compiler upgrades. #include <stdlib.h> #include <unistd.h> #include <string.h> #include <sched.h> #define DWORD unsigned long #else #include <windows.h> #endif #include <stdio.h> #include <assert.h rel='nofollow' onclick='return false;'> char g_s3Levels[2048]; // // CpuIDSupported will return 0 if CPUID instruction is unavailable. Otherwise, it will return // the maximum supported standard function. // unsigned int CpuIDSupported(void) { unsigned int MaxInputValue; // If CPUID instruction is supported #ifdef LINUX try { MaxInputValue = 0; // call cpuid with eax = 0 asm ( "xorl %%eax,%%eax\n\t" "cpuid\n\t" : "=a" (MaxInputValue) : : "%ebx", "%ecx", "%edx" ); } catch (...) { return(0); // cpuid instruction is unavailable } #else //Win32 try { MaxInputValue = 0; // call cpuid with eax = 0 __asm { xor eax, eax cpuid mov MaxInputValue, eax } } catch (...) { return(0); // cpuid instruction is unavailable } #endif return MaxInputValue; } // // GenuineIntel will return 0 if the processor is not a Genuine Intel Processor // unsigned int GenuineIntel(void) { #ifdef LINUX unsigned int VendorIDb = 0,VendorIDd = 0, VendorIDc = 0; try // If CPUID instruction is supported { // Get vendor id string asm ( //get the vendor string // call cpuid with eax = 0 "xorl %%eax, %%eax\n\t" "cpuid\n\t" : "=b" (VendorIDb), "=d" (VendorIDd), "=c" (VendorIDc) : : "%eax" ); } catch(...) { return(0); // cpuid instruction is unavailable } return ( (VendorIDb == 'uneG') && (VendorIDd == 'Ieni') && (VendorIDc == 'letn')); #else unsigned int VendorID[3] = {0, 0, 0}; try // If CPUID instruction is supported { __asm { xor eax, eax // call cpuid with eax = 0 cpuid // Get vendor id string mov VendorID, ebx mov VendorID + 4, edx mov VendorID + 8, ecx } } catch (...) { return(0); unsigned int MaxInputValue =0; // cpuid instruction is unavailable } return ( (VendorID[0] == 'uneG') && (VendorID[1] == 'Ieni') && (VendorID[2] == 'letn')); #endif } // // Function returns the maximum cores per physical package. Note that the number of // AVAILABLE cores per physical to be used by an application might be less than this // maximum value. // unsigned int MaxCorePerPhysicalProc(void) { unsigned int Regeax = 0; if (!HWD_MTSupported()) return (unsigned int) 1; // Single core #ifdef LINUX { asm ( "xorl %eax, %eax\n\t" "cpuid\n\t" "cmpl $4, %eax\n\t" // check if cpuid supports leaf 4 "jl .single_core\n\t" // Single core "movl $4, %eax\n\t" "movl $0, %ecx\n\t" // start with index = 0; Leaf 4 reports ); // at least one valid cache level asm ( "cpuid" : "=a" (Regeax) : : "%ebx", "%ecx", "%edx" ); asm ( "jmp .multi_core\n" ".single_core:\n\t" "xor %eax, %eax\n" ".multi_core:" ); } #else __asm { xor eax, eax cpuid cmp eax, 4 // check if cpuid supports leaf 4 jl single_core // Single core mov eax, 4 mov ecx, 0 // start with index = 0; Leaf 4 reports cpuid // at least one valid cache level mov Regeax, eax jmp multi_core single_core: xor eax, eax multi_core: } #endif return (unsigned int)((Regeax & NUM_CORE_BITS) >> 26)+1; } // // The function returns 0 when the hardware multi-threaded bit is not set. // unsigned int HWD_MTSupported(void) { unsigned int Regedx = 0; if ((CpuIDSupported() >= 1) && GenuineIntel()) { #ifdef LINUX asm ( "movl $1,%%eax\n\t" "cpuid" : "=d" (Regedx) : : "%eax","%ebx","%ecx" ); #else __asm { mov eax, 1 cpuid mov Regedx, edx } #endif } return (Regedx & HWD_MT_BIT); } // // Function returns the maximum logical processors per physical package. Note that the number of //
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