dds.rar

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基于FPGA的直接数字频率合成器(DDS)的设计
dds.rar
  • dds
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library ieee;---------顶层程序 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dds is port(k: in std_logic_vector(31 downto 0); n: in std_logic_vector(31 downto 0); clk:in std_logic; en:in std_logic; reset:in std_logic; p:out std_logic_vector(31 downto 0)); end entity dds; architecture art of dds is component sum32 is port(k: in std_logic_vector(31 downto 0); clk:in std_logic; en:in std_logic; reset:in std_logic; out1:out std_logic_vector(31 downto 0)); end component sum32; component reg1 is port(d: in std_logic_vector(31 downto 0); clk:in std_logic; q:out std_logic_vector(31 downto 0)); end component reg1; component adder32 is port(a: in std_logic_vector(31 downto 0); n: in std_logic_vector(31 downto 0); clk:in std_logic; en:in std_logic; out2:out std_logic_vector(31 downto 0)); end component adder32; component reg2 is port(e: in std_logic_vector(31 downto 0); clk:in std_logic; p:out std_logic_vector(31 downto 0)); end component reg2; signal s1:std_logic_vector(31 downto 0); signal s2:std_logic_vector(31 downto 0); signal s3:std_logic_vector(31 downto 0); begin u0:sum32 port map(k=>k,en=>en,reset=>reset,clk=>clk,out1=>s1); u1:reg1 port map(d=>s1,clk=>clk,q=>s2); u2:adder32 port map(a=>s2,en=>en,clk=>clk,n=>n,out2=>s3); u3:reg2 port map(e=>s3,clk=>clk,p=>p); end architecture art; library ieee;---------32位累加器 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sum32 is port(k: in std_logic_vector(31 downto 0); clk:in std_logic; en:in std_logic; reset:in std_logic; out1:out std_logic_vector(31 downto 0)); end entity sum32; architecture art of sum32 is signal temp:std_logic_vector(31 downto 0); begin process(clk,en,reset) is begin if reset='1'then temp<="00000000000000000000000000000000"; else if clk'event and clk='1'then if en='1'then temp<=temp+k; end if; end if; end if; out1<=temp; end process; end architecture art; library ieee;-------寄存器1 use ieee.std_logic_1164.all; entity reg1 is port(d: in std_logic_vector(31 downto 0); clk:in std_logic; q:out std_logic_vector(31 downto 0)); end entity reg1; architecture art of reg1 is begin process(clk) is begin if clk'event and clk='1'then q<=d; end if; end process; end architecture art; library ieee;----------------32位加法器 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder32 is port(n: in std_logic_vector(31 downto 0); a: in std_logic_vector(31 downto 0); clk:in std_logic; en:in std_logic; out2:out std_logic_vector(31 downto 0)); end entity adder32; architecture art of adder32 is signal b:std_logic_vector(31 downto 0); begin process(clk,en) is begin if clk'event and clk='1'then if en='1'then b<=a+n; end if; end if; out2<=b; end process; end architecture art; library ieee;---------------寄存器2 use ieee.std_logic_1164.all; entity reg2 is port(e: in std_logic_vector(31 downto 0); clk:in std_logic; p:out std_logic_vector(31 downto 0)); end entity reg2; architecture art of reg2 is begin process(clk) is begin if clk'event and clk='1'then p<=e; end if; end process; end architecture art;
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