exp1.rar

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  • 2009-11-26 16:38
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program code to output analog values in TMS320C50 processor
exp1.rar
  • exp1
  • Debug
  • exp1.out
    3KB
  • exp1.map
    3.9KB
  • sys_init.obj
    833B
  • vector.obj
    1.2KB
  • dac.obj
    1KB
  • iecex1.obj
    1.1KB
  • vector.asm
    1.8KB
  • exp1.paf
    1.9KB
  • f2407.h
    15.6KB
  • Debug.lkv
    288B
  • iecex1.asm
    3.8KB
  • Debug.lkf
    288B
  • exp1.pjt
    763B
  • dac.asm
    1.8KB
  • sys_init.asm
    3.1KB
  • 2407.cmd
    1.4KB
  • cc_build_Debug.log
    835B
内容介绍
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| ;Filename: f2407.h | ; | ;Author: David M. Alter, Texas Instruments Inc. | ; | ;Description: LF2407 DSP register definitions for assembly code | ; | ;History: 03/14/01 - Original. (D. Alter) | ; 08/12/02 - Fixed addresses of CAP2FBOT, CAP3FBOT, | ; CAP5FBOT, and CAP6FBOT. (D. Alter) | ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ;Select PLL multiplication ratio ;x2_PLL .set 1 ;x4_PLL .set 0 ;Core registers IMR .set 0004h ;Interrupt mask reg GREG .set 0005h ;Global memory allocation reg IFR .set 0006h ;Interrupt flag reg ;System configuration and interrupt registers PIRQR0 .set 7010h ;Peripheral interrupt request reg 0 PIRQR1 .set 7011h ;Peripheral interrupt request reg 1 PIRQR2 .set 7012h ;Peripheral interrupt request reg 2 PIACKR0 .set 7014h ;Peripheral interrupt acknowledge reg 0 PIACKR1 .set 7015h ;Peripheral interrupt acknowledge reg 1 PIACKR2 .set 7016h ;Peripheral interrupt acknowledge reg 2 SCSR1 .set 7018h ;System control & status reg 1 SCSR2 .set 7019h ;System control & status reg 2 DINR .set 701Ch ;Device identification reg PIVR .set 701Eh ;Peripheral interrupt vector reg ;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ RTI_CNTR .set 07021h ; RTI Counter reg WD_CNTR .set 07023h ; WD Counter reg WD_KEY .set 07025h ; WD Key reg WDKEY .set WD_KEY RTI_CNTL .set 07027h ; RTI Control reg WD_CNTL .set 07029h ; WD Control reg WDCR .set WD_CNTL PLL_CNTL1 .set 0702Bh ; PLL control reg 1 PLL_CNTL2 .set 0702Dh ; PLL control reg 2 ;Watchdog timer (WD) registers ;WDCNTR .set 7023h ;WD counter reg ;WDKEY .set 7025h ;WD reset key reg ;WDCR .set 7029h ;WD timer control reg ;Serial Peripheral Interface (SPI) registers SPICCR .set 7040h ;SPI configuration control reg SPICTL .set 7041h ;SPI operation control reg SPISTS .set 7042h ;SPI status reg SPIBRR .set 7044h ;SPI baud rate reg SPIRXEMU .set 7046h ;SPI emulation buffer reg SPIRXBUF .set 7047h ;SPI serial receive buffer reg SPITXBUF .set 7048h ;SPI serial transmit buffer reg SPIDAT .set 7049h ;SPI serial data reg SPIPRI .set 704Fh ;SPI priority control reg ;SCI registers SCICCR .set 7050h ;SCI communication control reg SCICTL1 .set 7051h ;SCI control reg 1 SCIHBAUD .set 7052h ;SCI baud-select reg, high bits SCILBAUD .set 7053h ;SCI baud-select reg, low bits SCICTL2 .set 7054h ;SCI control reg 2 SCIRXST .set 7055h ;SCI receiver status reg SCIRXEMU .set 7056h ;SCI emulation data buffer reg SCIRXBUF .set 7057h ;SCI receiver data buffer reg SCITXBUF .set 7059h ;SCI transmit data buffer reg SCIPRI .set 705Fh ;SCI priority control reg ;External interrupt configuration registers XINT1CR .set 7070h ;Ext interrupt 1 config reg XINT2CR .set 7071h ;Ext interrupt 2 config reg ;Digital I/O registers MCRA .set 7090h ;I/O mux control reg A MCRB .set 7092h ;I/O mux control reg B MCRC .set 7094h ;I/O mux control reg C PADATDIR .set 7098h ;I/O port A data & dir reg PBDATDIR .set 709Ah ;I/O port B data & dir reg PCDATDIR .set 709Ch ;I/O port C data & dir reg PDDATDIR .set 709Eh ;I/O port D data & dir reg PEDATDIR .set 7095h ;I/O port E data & dir reg PFDATDIR .set 7096h ;I/O port F data & dir reg ;Analog-to-Digital Converter (ADC) registers ADCTRL1 .set 70A0h ;ADC control reg 1 ADCTRL2 .set 70A1h ;ADC control reg 2 MAXCONV .set 70A2h ;Maximum conversion channels reg CHSELSEQ1 .set 70A3h ;Channel select sequencing control reg 1 CHSELSEQ2 .set 70A4h ;Channel select sequencing control reg 2 CHSELSEQ3 .set 70A5h ;Channel select sequencing control reg 3 CHSELSEQ4 .set 70A6h ;Channel select sequencing control reg 4 AUTO_SEQ_SR .set 70A7h ;Autosequence status reg RESULT0 .set 70A8h ;Conversion result buffer reg 0 RESULT1 .set 70A9h ;Conversion result buffer reg 1 RESULT2 .set 70AAh ;Conversion result buffer reg 2 RESULT3 .set 70ABh ;Conversion result buffer reg 3 RESULT4 .set 70ACh ;Conversion result buffer reg 4 RESULT5 .set 70ADh ;Conversion result buffer reg 5 RESULT6 .set 70AEh ;Conversion result buffer reg 6 RESULT7 .set 70AFh ;Conversion result buffer reg 7 RESULT8 .set 70B0h ;Conversion result buffer reg 8 RESULT9 .set 70B1h ;Conversion result buffer reg 9 RESULT10 .set 70B2h ;Conversion result buffer reg 10 RESULT11 .set 70B3h ;Conversion result buffer reg 11 RESULT12 .set 70B4h ;Conversion result buffer reg 12 RESULT13 .set 70B5h ;Conversion result buffer reg 13 RESULT14 .set 70B6h ;Conversion result buffer reg 14 RESULT15 .set 70B7h ;Conversion result buffer reg 15 CALIBRATION .set 70B8h ;Calibration result reg ;Controller Area Network (CAN) registers MDER .set 7100h ;CAN mailbox direction/enable reg TCR .set 7101h ;CAN transmission control reg RCR .set 7102h ;CAN receive control reg MCR .set 7103h ;CAN master control reg BCR2 .set 7104h ;CAN bit config reg 2 BCR1 .set 7105h ;CAN bit config reg 1 ESR .set 7106h ;CAN error status reg GSR .set 7107h ;CAN global status reg CEC .set 7108h ;CAN trans and rcv err counters CAN_IFR .set 7109h ;CAN interrupt flag reg CAN_IMR .set 710Ah ;CAN interrupt mask reg LAM0_H .set 710Bh ;CAN local acceptance mask MBX0/1 LAM0_L .set 710Ch ;CAN local acceptance mask MBX0/1 LAM1_H .set 710Dh ;CAN local acceptance mask MBX2/3 LAM1_L .set 710Eh ;CAN local acceptance mask MBX2/3 MSGID0L .set 7200h ;CAN message ID for mailbox 0 (lower 16 bits) MSGID0H .set 7201h ;CAN message ID for mailbox 0 (upper 16 bits) MSGCTRL0 .set 7202h ;CAN RTR and DLC for mailbox 0 MBX0A .set 7204h ;CAN 2 of 8 bytes of mailbox 0 MBX0B .set 7205h ;CAN 2 of 8 bytes of mailbox 0 MBX0C .set 7206h ;CAN 2 of 8 bytes of mailbox 0 MBX0D .set 7207h ;CAN 2 of 8 bytes of mailbox 0 MSGID1L .set 7208h ;CAN message ID for mailbox 1 (lower 16 bits) MSGID1H .set 7209h ;CAN message ID for mailbox 1 (upper 16 bits) MSGCTRL1 .set 720Ah ;CAN RTR and DLC for mailbox 1 MBX1A .set 720Ch ;CAN 2 of 8 bytes of mailbox 1 MBX1B .set 720Dh ;CAN 2 of 8 bytes of mailbox 1 MBX1C .set 720Eh ;CAN 2 of 8 bytes of mailbox 1 MBX1D .set 720Fh ;CAN 2 of 8 bytes of mailbox 1 MSGID2L .set 7210h ;CAN message ID for mailb
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