FLASH_WRITE_of_MSP430.rar - This program first erases flash seg C, then it increments all
values in seg C, then it erases seg D, then copies seg C to seg D. Seg C @ 1040h
Seg D @ 1000h
The EEI bit is set for the Flash Erase Cycles. This does allow the Timer_A
Interrupts to be handled also during the Segment erase time.
ACLK = n/a, MCLK = SMCLK = CALxxx_1MHZ = 1MHz
,2017-06-01 18:57:31,下载1次
UART_of_MSP430F249.rar - Echo a received character, RX ISR used. Normal mode is LPM0.
USCI_A0 RX interrupt triggers TX Echo.
Baud rate divider with 1MHz = 1MHz/19200 = ~52.1
ACLK = n/a, MCLK = SMCLK = CALxxx_1MHZ = 1MHz
,2017-06-01 18:52:45,下载1次
SPI_of_MSP430F249.rar - SPI master talks to SPI slave using 3-wire mode. Incrementing
data is sent by the master starting at 0x01. Received data is expected to
be same as the previous transmission TXData = RXData-1.
USCI RX ISR is used to handle communication with the CPU, normally in LPM0.
ACLK = ~32.768kHz, MCLK = SMCLK = DCO ~ 1MHz. BRCLK = ACLK/2.
,2017-06-01 18:46:45,下载1次
I2C_of_MSP430F249.rar - This demo connects two MSP430 s via the I2C bus. The master
reads 5 bytes the slave. This is the MASTER CODE. The data the slave
transmitter begins at 0 and increments with each transfer.
The USCI_B0 RX interrupt is used to know when new data has been received.
ACLK = default REFO ~32768Hz, MCLK = SMCLK = BRCLK = DCODIV ~1MHz.
,2017-06-01 18:44:47,下载1次
TimerA_of_MSPF249.rar - Toggle P1.0 using software and the TA_0 ISR. Timer_A is
configured for up mode, thus the timer overflows when TAR counts
to CCR0. In this example, CCR0 is loaded with 1000-1.
ACLK = TACLK = INCLK = 32768Hz, MCLK = SMCLK = default DCO ~1.045Mhz
,2017-06-01 18:42:57,下载1次
ADC_of_MSP430F249.rar - A single sample is made on A10 with reference to internal
1.5V Vref. Software sets ADC12SC to start sample and conversion - ADC12SC
automatically cleared at EOC. ADC12 internal oscillator times sample
and conversion. In Mainloop MSP430 waits in LPM0 to save power until
ADC10 conversion complete, ADC12_ISR will force exit any LPMx in
Mainloop on reti.,2017-06-01 18:38:40,下载2次