digital_design.rar - digital_design，精品电子书,2007-11-27 10:51:12,下载5次
VerilogHDL_advanced_digital_design_code_Ch7.rar - VerilogHDL_advanced_digital_design_code_Ch7
Verilog HDL 高级数字设计 源码ch7,2007-11-27 10:15:37,下载16次
VerilogHDL_advanced_digital_design_code_Ch6.rar - VerilogHDL_advanced_digital_design_code_Ch6
Verilog HDL 高级数字设计源码ch6,2007-11-27 10:13:37,下载13次
VerilogHDL_advanced_digital_design_code_Ch5.rar - Verilog HDL 高级数字设计源码 _chapter5,2007-11-27 10:12:02,下载14次
VerilogHDL_advanced_digital_design_code_Ch4.rar - Verilog HDL 高级数字设计源码 _chapter4,2007-11-27 10:10:43,下载11次
Content_Addressable_Memory.rar - Content Addressable Memory 的verilog源代码。经过modelsim仿真。,2007-11-27 10:00:58,下载16次
Synthesizable_FIFO_verilog.rar - Synthesizable FIFO Model
This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
,2007-11-27 09:57:59,下载46次
Synchronous_read_write_RAM.rar - Synchronous read write RAM verilog。经过modelsim se仿真。,2007-11-27 09:52:42,下载93次
Asynchronous_read_write_RAM.rar - Dual Port RAM
Asynchronous Read/Write
经过modelsim仿真
,2007-11-27 09:48:50,下载66次