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ima_adpcm_encoder_latest.tar.gz - This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.,2009-04-17 14:11:13,下载74次
pif2wb_latest.tar.gz - This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.,2009-04-17 14:06:35,下载8次
pcie_vera_tb_latest.tar.gz - FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs ,2009-04-17 13:58:23,下载50次
pit_latest.tar.gz - Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done,2009-04-17 12:22:22,下载10次
hssdrc_latest.tar.gz - HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License,2009-04-17 12:18:02,下载38次
hilbert_transformer_latest.tar.gz - The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput. ,2009-04-17 12:14:25,下载78次
adaptive_lms_equalizer_latest.tar.gz - In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic. ,2009-04-17 12:12:01,下载66次
twofish_latest.tar.gz - VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in library-like form All needed components up to, including the round/key schedule circuits are implemented, giving the flexibility to be combined in different architectures (iterative, rolled out/pipelined etc). Manual in English is included with more details about how to use the components and/or how to optimize some of them. All testbenches are provided (tables, variable key/text, ECB/CBC monte carlo) for 128, 192 and 256 bit key sizes, along with their respective vector files.,2009-04-17 12:10:03,下载19次
aes_crypto_core_latest.tar.gz - Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added ,2009-04-17 12:06:20,下载133次
wb_lpc_latest.tar.gz - Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.,2009-04-17 11:13:46,下载31次
uart16750_latest.tar.gz - Implements a 16550/16750 UART core,2009-04-17 11:09:55,下载40次

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