上传列表：

kogge_stone_adder.rar - kogge stone adder generic..,2018-01-10 19:27:11,下载2次
csa_codes.rar - carry_select_adder for 16-bit in verilog,2018-01-10 18:48:37,下载1次
SPANING_27BIT.rar - spanning tree adder writtern vHDL Code,2018-01-10 18:20:58,下载1次
qam16 modulator.rar - QAM16 MODULATOR VERILOG CODE ON FPGA,2017-06-05 20:32:44,下载4次
fir filter design.rar - FIR FILTER DESIGN IN VERILOG ON FPGA,2017-06-05 20:29:47,下载12次
reconf. router code xylinx.zip - design and fpga implementation of Routing algorithm for NOC,2017-06-05 20:24:23,下载14次
16x 16 vedic mulbit.zip - vedic 16x16 design and teshbench fully working codes..,2017-06-05 20:18:41,下载3次
hp and lp filter.rar - hp and lp filter verilog code..,2017-06-05 20:15:53,下载4次
FLOATING-BUFFER.rar - Floating Buffer verilog code for NOC design used for dynamic reconfiguration.,2016-05-23 15:39:00,下载4次
QAM-16-OFDM_Module.rar - QAM16-verilog code for OFDM module. includes mapping design,2016-05-23 15:36:18,下载10次
adcdac_modify.rar - ADC-DAC VHDL Working code for Spartan 3/3E FPGA device,2016-05-23 15:33:20,下载6次
PHASE_ACCUMULATOR.rar - PHASE Accumulator for DFS. VHDL full working codes..,2016-05-23 15:30:31,下载1次
CORDIC_CODES_NEW.rar - Cordic VHDL codes full working..,2016-05-23 15:26:19,下载1次
mac_unit_vhdl.rar - MAC UNIT DESIGN IN VHDL..,2015-06-30 13:31:14,下载4次
counters.rar - DIFFERNT TYPES OF COUNTERS,2015-06-30 13:27:19,下载1次
verilog.rar - BASIC VERILOG CODES ..,2015-06-30 13:26:01,下载2次

近期下载：

ofdmsjsu.rar - its a ofdma simulink model. with a modulation scheme on 8psk
fft_64.rar - fft processor for ofdma system
Energy-harvesting-Coding-with-Matlab.rar - 能量采集系统仿真程序！能量采集系统仿真程序！能量采集系统仿真程序！能量采集系统仿真程序！
CNN-FPGA-master.zip - 用FPGA实现CNN算法，实现CNN加速
Hardware-CNN-master.zip - Convolutional neural network code for fpga
CNN.zip - THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。
bch_enc.zip - bch编码模块，verilog程序，串行输入，串行输出
BCH_dec_verilog.rar - BCH decoder based on Verilog design
bch_verilog.rar - bch(255,239)编码算法的verilog实现，综合仿真通过，与matlab仿真的结果一致
DPSK_modulate.zip - verilog实现DPSK的调制是基于DDS直接频率生成
BCH-rtl-sourcecode.zip - BCH RTL 源代码，内容包括解码和编码，适合应用在需要纠错的芯片产品，已经在实际的芯片验证
BCH.zip - BCH解码与编码的verilog语言实现
bch_dec_enc_dcd_latest.tar.gz - BCH译码器设计源代码，它能实现对两位错误的纠正。这是最新版本。
bchencodeanddecodewitcorrection.rar - bch encode and decode wit error correction for bch(255,233)
Bch15_5.zip - The attached file consists of implimentation of BCH codes in VHDL programming using XILINX software. This code will reduce the no. of gates requirement.
BCHdecode.rar - BCH(63,56) decode,verilog
projectp20wtlsp20finalp20report[1].rar - wireless body area network
SVPWM_FPGA_ContainSourceCode.zip - 广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。
Two_Level_SVPWM.rar - 代码为两电平SVPWM调制算法的Verilog程序。包括扇区划分、时间计算、死区控制等。
svpwm_full_nios.rar - 实现verilog的svpwm 对于算法开发有很好的帮助。。希望大家多多学习了。

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